Debate rages about which approach is better for SoC design: simulation, or emulation. Simulation proponents point to software saving the need for expensive hardware platforms. Emulation supporters stake their claims on accuracy and the incorporation of real-time I/O. A few years back, some creative types coined the term SEmulation, a hybrid utilizing both approaches. A quick search turns up an Altera white paper on that exact topic, circa 2007, and an even older reference of first usage of the term in EDA around the year 2000.
Funky names aside, the drawback with most early-stage approaches to any complex problem is they are proprietary. A particular simulator environment was lashed to a certain model of FPGA-based hardware prototyping platform, with a high degree of knowledge about the internals of each required to make it work. A handy idea, but potentially expensive, inflexible, and locked in.
2007 is right about the time the SCE-MI specification was emerging in original form from Accellera. SCE-MI standardizes the co-emulation modeling interface. It also spends a lot of effort on minimizing the interaction, or synchronizations, required between the simulator and emulator platform. Simulators like events, where emulators prefer timed sequences.
SCE-MI establishes the idea of transactors, connecting an untimed testbench in the simulator to timed modules in the emulator. This allows the emulator to run with its faster timing intact. Transactors form a pontoon bridge of sorts. By adhering to the SCE-MI standard, a simulator and emulator are loosely coupled, allowing replacement of one or both sides by adding the proper transactors. Internal knowledge is reduced, flexibility is greatly increased, and lock-in is avoided.
Aldec has taken a big step forward with the latest release of their hardware emulation solution software. HES-DVM brings a powerful simulation environment compliant with SCE-MI. It allows connection of the Aldec HES-7 FPGA-based prototyping system, or another third-party SCE-MI compliant platform, or custom in-house FPGA hardware to provide the hardware acceleration.
Users of UVM need hardware acceleration, desperately. Even with continual improvements in constrained random solvers and other algorithms, HDL simulators are still compute-intensive beasts. As the size of the design increases, the execution time of the simulation goes up dramatically. Using an FPGA-based system provides speed effective acceleration for an HDL simulator without the massive costs of a full-blown hardware emulator.
HES-DVM 2014.12 brings improvements in three main areas:
- Significant improvements in the SCE-MI 2 Compiler expand capability to convert behavioral code into synthesizable RTL targeting an FPGA. For example, the compiler now supports SystemVerilog DPI-C import and exports as a SCE-MI function-based interface. Support for plusargs has been added, allowing arguments to be passed within transactors, aiding in run-time configurable parameterization. Turbo Mode allows compression of design clocks so edge sequences are preserved, but periods are shortened. Force signal values can send values to force any design net in RTL. Optimization has been applied to constant arguments of DPI-C function calls, reducing synchronization and speeding up emulation.
- Scalability improvements allow jobs to be scheduled against load sharing facility (LSF) compute farms. This also applies to scaling of acceleration clusters using multiple HES-7 or similar platfforms.
- Support has been added for the Cadence “NCSim” simulator, part of Cadence Incisive Enterprise Simulator. The DVM generates the SCE-MI DPI emulation bridge compatible with NCSim, and creating a new project or simulation options can select NCSim.
Embracing SCE-MI and adding hardware acceleration dramatically increases the “return on simulation” for ASIC developers. Aldec continues to open their environment, combining their tools, popular tools from other EDA vendors, and custom hardware platforms into a complete solution for RTL verification.