WP_Term Object
(
    [term_id] => 34
    [name] => Ansys, Inc.
    [slug] => ansys-inc
    [term_group] => 0
    [term_taxonomy_id] => 34
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 195
    [filter] => raw
    [cat_ID] => 34
    [category_count] => 195
    [category_description] => 
    [cat_name] => Ansys, Inc.
    [category_nicename] => ansys-inc
    [category_parent] => 157
)
            
ideas on demand banner 800x100 20201218
WP_Term Object
(
    [term_id] => 34
    [name] => Ansys, Inc.
    [slug] => ansys-inc
    [term_group] => 0
    [term_taxonomy_id] => 34
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 195
    [filter] => raw
    [cat_ID] => 34
    [category_count] => 195
    [category_description] => 
    [cat_name] => Ansys, Inc.
    [category_nicename] => ansys-inc
    [category_parent] => 157
)

Analyze Substrate Noise in SoC Design?

Analyze Substrate Noise in SoC Design?
by Pawan Fangaria on 01-19-2015 at 4:00 pm

Often substrate noise analysis takes place when everything is there on the chip, but that stage comes near the tape-out which is too late to make major changes in architecture, placement, introducing noise protection circuitry for the victims and so on. It was okay when there used to be very little analog content on the chip. But in today’s SoC where substantial analog and RF content (that may be in the form of specialized IP) can be there on the chip intermingled with large digital content, there is no concession to wait till tape-out risking the schedule because increasing substrate noise can pose severe risks to those sensitive IP blocks. There may be multiple RF circuits operating in close proximity with fast switching circuits, specifically in wireless applications. If not controlled properly, substrate noise can severely affect performance of SoCs.

Although analog and digital blocks have separate power and ground supply structures, they are etched on a common silicon substrate, thus allowing the generated noise to propagate through the substrate. There are isolation techniques to separate these two types of circuits, but how to determine which technique and how much control is appropriate in a particular situation, such that the SoC is neither overdesigned nor left susceptible to substrate noise that can limit its performance? There is a need to accurately model and predict the substrate coupled noise and add appropriate isolation structures to design a robust SoC.

Ansys’s Totem-SE supports different isolation structures in its analysis that include P+ guard-ring, N+ guard-ring, N-well wall, Deep N-well wall, and Deep N-well pocket. Totem-SE considers all substrate layers and necessary technology parameters in constructing the substrate RC network and models all pertinent noise injection elements such as standard cells, memories, IOs, and specific analog and custom circuits, thus providing accurate analysis of right fitment of different isolation structures in typical scenarios.

Experimental results with different isolation structures between a digital processor core and an analog block show close correlation between measurement from silicon (blue waveform) and the prediction from Totem-SE (pink waveform). The waveform indicates the worst noise amplitude starting from digital circuit, going through different isolation structures, into the analog circuit. Totem-SE can also provide DvD (Dynamic Voltage Drop) maps for various substrate layers for designers to determine optimal locations for isolation and protection structures in their designs.

Totem-SE can be used for full-chip analysis in which the noise injection from various digital and analog components are modeled and propagated through the on-die, package and substrate parasitic network. The noise waveforms from the full-chip analysis can be captured at specific locations of an analog block and used as PWL input to the IP level timing and functional simulations using Spice to improve accuracy of the IP level simulation. By using the true voltage noise signature, the impact of the coupled noise on the IP can be explored to determine if additional changes in the layout or protection schemes are needed, thereby preventing silicon issues after tape-out.

In an SoC design, the noise generated by a digital circuit can be controlled by several means including isolation/protection structures, decoupling capacitances, power grid robustness, number of active blocks and activities on the blocks, and distance from active elements. Totem-SE is very versatile to be used in various customer specific SoC design flows to start substrate noise analysis as early as possible. Ansys provides a whole range of tool suite for power, noise, reliability analysis and optimization of SoCs by all means.

Hagay Guterman from CSRand Jerome Toublanc from Ansyswill be presenting a joint paperin DesignCon 2015, in which they will present a novel proven design flow which starts substrate analysis very early in the design stage, even with very basic chip information. The models of noise generation and noise propagation through the substrate can develop in parallel to each other when relevant data is available.

Do reserve your seat for the following session/paper in DesignCon 2015 to know more –

Session Code: 2-TH4
Track Name: 02 Analog and Mixed-Signal Modeling and Simulation Challenges
Paper Title: Substrate Noise Full-chip Level Analysis Flow from Early Design Stages Till Tapeout
Date: January 29, Thursday
Time: 11:05 AM – 11:45 AM

More Articles by PawanFangaria…..

Share this post via:

Comments

0 Replies to “Analyze Substrate Noise in SoC Design?”

You must register or log in to view/post comments.