CEO Interview with Dr. Stefan Pastine of Thintronics

CEO Interview with Dr. Stefan Pastine of Thintronics
by Daniel Nenni on 09-27-2026 at 8:00 am

Stefan Pastine

Stefan Pastine PhD is an American chemist and entrepreneur. In 2011, he founded Connora Technologies, developer of Recyclamine, a recyclable epoxy thermoset technology that allows carbon fiber, fiberglass, and aramid fiber to be recovered from composite waste. Aditya Birla Chemicals acquired Connora in 2019 and applied … Read More


I will see you at the Substrate Vision Summit in Santa Clara

I will see you at the Substrate Vision Summit in Santa Clara
by Daniel Nenni on 11-20-2024 at 10:00 am

Soitec Substrate Vision Summit

WIth packaging being one of the top sources of traffic on SemiWiki, I am expecting a big crowd at this event. A semiconductor substrate is a foundational material used in the fabrication of semiconductor devices. Substrates are a critical part of the manufacturing process and directly affect the performance, reliability, and… Read More


Maximizing ASIC Performance through Post-GDSII Backend Services

Maximizing ASIC Performance through Post-GDSII Backend Services
by Kalar Rajendiran on 03-04-2021 at 6:00 am

Panel 1 Alchip – HPC ASIC Manufacturing Done Your Way 1030x579 1

ASICs by definition are designed to meet the respective applications’ requirements. ASIC engineers deploy various design techniques to maximize performance, minimize power and reduce chip size. But is there more that can be done after the GDSII is taped out? A recent press release from Alchip Technology dated Feb 4, 2021 claims… Read More


Synopsys’ New Die-to-Die PHY IP – What It Means

Synopsys’ New Die-to-Die PHY IP – What It Means
by Randy Smith on 10-29-2019 at 10:00 am

This morning, Synopsys announced its new Die-to-Die PHY IP. This announcement is critically important as it addresses two major market drivers – the growing need for faster connectivity in the datacenter and similar markets, and a path to better exploit the latest processes by dealing with yield issues for larger dies in a different… Read More


Analyze Substrate Noise in SoC Design?

Analyze Substrate Noise in SoC Design?
by Pawan Fangaria on 01-19-2015 at 4:00 pm

Often substrate noise analysis takes place when everything is there on the chip, but that stage comes near the tape-out which is too late to make major changes in architecture, placement, introducing noise protection circuitry for the victims and so on. It was okay when there used to be very little analog content on the chip. But … Read More