Getting Started with ANSYS Totem

Getting Started with ANSYS Totem
by Admin on 03-24-2020 at 9:30 am

March 24, 2020

9:30 AM – 2:30 PM (PDT)

Venue:
ANSYS, Inc.
2645 Zanker Road
San Jose, CA 95134
USA

Contact:

Phoebe Lee

phoebe.lee@ansys.com

Join us for a free hands-on workshop to learn how to perform on chip static and dynamic voltage drop analysis, electromigration, design weakness and hot spot analysis using ANSYS Totem. … Read More


Reliability Signoff for FinFET Designs

Reliability Signoff for FinFET Designs
by Bernard Murphy on 10-17-2017 at 7:00 am

Ansys recently hosted a webinar on reliability signoff for FinFET-based designs, spanning thermal, EM, ESD, EMC and aging effects. I doubt you’re going to easily find a more comprehensive coverage of reliability impact and analysis solutions. If you care about reliability in FinFET designs, you might want to check out this webinar.… Read More


Integrity and Reliability in Analog and Mixed-Signal

Integrity and Reliability in Analog and Mixed-Signal
by Bernard Murphy on 07-18-2016 at 1:30 pm

In the largest and fastest growing categories in electronics – mobile, IoT and automotive – analog is playing an increasingly important role. It’s important in delivering high integrity power and critical signals to the design though LDO regulators and PLLs, in managing high speed interfaces like DDR and SERDES, in interfacing… Read More


ANSYS Enters the League of 10nm Designs with TSMC

ANSYS Enters the League of 10nm Designs with TSMC
by Pawan Fangaria on 04-09-2015 at 7:00 pm

The way we are seeing technology progression these days is unprecedented. It’s just about six months ago, I had written about the intense collaboration between ANSYSand TSMCon the 16nm FinFET based design flow and TSMC certifying ANSYS tools for TSMC 16nm FF+ technology and also conferring ANSYS with “Partner of the Year” award.… Read More


FinFET Designs Need Early Reliability Analysis

FinFET Designs Need Early Reliability Analysis
by Pawan Fangaria on 02-19-2015 at 9:30 pm

In a world with mobile and IoT devices driven by ultra-low power, high performance and small footprint transistors, FinFET based designs are ideal. FinFETs provide high current drive, low leakage and high device density. However, a FinFET transistor is more exposed to thermal issues, electro migration (EM), and electrostatic… Read More


Analyze Substrate Noise in SoC Design?

Analyze Substrate Noise in SoC Design?
by Pawan Fangaria on 01-19-2015 at 4:00 pm

Often substrate noise analysis takes place when everything is there on the chip, but that stage comes near the tape-out which is too late to make major changes in architecture, placement, introducing noise protection circuitry for the victims and so on. It was okay when there used to be very little analog content on the chip. But … Read More


Solution for PI, TI & SI Issues in 3D-ICs

Solution for PI, TI & SI Issues in 3D-ICs
by Pawan Fangaria on 11-30-2014 at 7:00 pm

As we move towards packing more and more functionalities and increasing densities of SoCs, the power, thermal and signal integrity issues keep on rising. 3D-IC is a great concept to stack multiple dies on top of each other vertically. While it brings lot of avenues to package dies with multiple functions together, it has challenges… Read More


ANSYS Tools Shine at FinFET Nodes!

ANSYS Tools Shine at FinFET Nodes!
by Pawan Fangaria on 09-30-2014 at 4:00 pm

In the modern semiconductor ecosystem we are seeing rapid advancement in technology breaking past once perceived limits; 28nm, 20nm, 16-14nm, 10nm and we are foreseeing 7nm now. Double and multi-patterning are already being seen along with complex FinFET structures in transistors to gain the ultimate advantages in PPA from… Read More


Know All About ESD and Save Your Chips & Systems

Know All About ESD and Save Your Chips & Systems
by Pawan Fangaria on 08-24-2014 at 7:30 pm

In this age of electronics, especially with so many different types of human held devices and more upcoming wearable devices, it’s utmost important to protect the massive circuitry inside those tiny parts in the devices from ESD related failures. The protection needs to happen at all stages – cells inside the chips, package… Read More


Electronic Thermal Management through Icepak

Electronic Thermal Management through Icepak
by Pawan Fangaria on 08-03-2014 at 8:30 pm

Last week my daughter was playing some games on my Google Nexus smartphone for a while when one of my friends called. When I picked up the phone, I couldn’t imagine it was so hot. There is no doubt; every electronic device today emits an order of magnitude higher heat than what it used to at most a decade ago. There is so much emphasis on … Read More