In the semiconductor industry, it feels great to hear about the process technology shrinking to lower nodes along with innovative transistor structures that offer major gains in PPA (Power, Performance and Area). However, it requires huge investment of capital, time and effort from foundries to conceptualize, prototype and prove such technology for production. In order to design large chips based on such technology, robust design automation tools are required that must confirm to the complex foundry rules and constraints imposed by such technology and also fulfil the challenging requirements of PPA and reliability for the chip. The key is to produce chips with high yield and reliability that lasts for long duration.
I think most of us know about Intel’s new fabrication technology for 3D transistors, popularly known as Tri-gate transistors which can have multiple source-drain channels and a vertical gate overlapping each channels from three sides, thus reducing leakage and power consumption significantly and increasing speed with quick switching of transistors. Since this technology is proven, we now have started hearing about reference flows for semiconductor designs involving various EDA tools qualified with this technology. I am particularly impressed with Ansysand Intelannouncementthis month about their production proven reference flow for ‘Power, EM and Reliability Sign-off’ of designs based on Intel’s 14nm Tri-gate process.
The reason I liked it is because very recently I blogged about Ansys’s RedHawk 2014 platform which addresses critical challenges of high density, high performance FinFET based designs to produce new generation of complex SoCs with high degree of reliability including power, noise, EM and ESD effects. Although FinFET and Tri-gate transistors have similar structure, it is important that Intel has qualified through its custom foundry the complete design flow based on its Tri-gate technology by involving multiple tools of Ansys and made it commercially available as reference flow for its custom foundry customers in the mobile and cloud market segments which typically need very low power consumption, high speed of operation and lower area. I’m sure this design flow and technology will prove beneficial for other market segments as well because most of the semiconductor designs are becoming PPA critical day-by-day.
This reference flow involves RedHawk[SUP]TM[/SUP]for SoC power and EM sign-off, Totem[SUP]TM[/SUP]for custom IP power and EM integrity, and PathFinder[SUP]TM[/SUP] for full-chip ESD validation, thus completing top to bottom flow for power, noise, EM and ESD reliability sign-off.
RedHawk provides chip, package and system level analysis and sign-off for dynamic power integrity, noise and reliability of low power, high performance SoCs. It checks for simultaneous switching noise, decoupling capacitance, package inductance, power and signal wire electromigration, ESD protection, RTL-to-GDS power closure and so on and signs off the design for power, noise and reliability with silicon correlated level of accuracy.
Totem is an ideal tool for IP sign-off with full-chip layout based power and noise analysis for mixed-signal designs. It can very effectively be used for early stage prototyping, designing of package and power network and signing off the chip with accuracy.
PathFinder provides ESD (Electro-static Discharge) integrity (with HBM and MM checks) to address much needed reliability of designs at such lower nodes. It can exhaustively analyze the whole design to identify potential weaknesses which may expose the chip to ESD related failure. It can be used from early prototyping to final sign-off stages of the chip to improve yield and eliminate conditions that can lead to any ESD event.
The confidence of this flow at 14nm Tri-gate process is much higher as it is production-proven and is an extension from the previous collaborative work of Intel and Ansys on 22nm technology. My feeling is that in coming days, this flow will prove very effective in bringing the main stream production on 14nm Tri-gate technology involving Ansys’s design and analysis tools for power, noise and reliability.
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