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Noise-Coupled Analysis for Automotive ICs at DAC

Noise-Coupled Analysis for Automotive ICs at DAC
by Daniel Payne on 06-20-2014 at 2:00 pm

My favorite method to learn about EDA tools at DAC is by listening to actual IC designers, so on June 3rd I heard Jacob Bakker from NXP talk about his experience with noise coupled analysis for advanced mixed-signal automotive ICs.

 automotive ics dac


NXP is #1 in automotive infotainment ASSPs (2 is STM, 3 is Renesas). One example is the design of an in-car digital radio by integrating all features onto a single chip. Challenges include interference spectrum, where spikes will reduce the performance and need to be avoided while serving markets like: Europe, Japan, USA. One chip serves all three frequency bands for highest cost effectiveness.

Substrate noise is one source that needs to be analyzed and then minimized. The digital switching can pump noise into the substrate, which then hurts the radio performance. To model the coupling requires simulation of the aggressor, propagation and victim. Design avoidance methods can protect the propagation and victim blocks.

Interference prevention is done at NXP with passive isolation structures, noise tolerant RF and analog IP blocks, finally digital blocks that generate minimal noise into the substrate. All three techniques are required.

Substrate noise can come from digital circuits that are switching ( L di/dt ). Adding decoupling capacitors can reduce this substrate noise. Ground bounce needs to be analyzed, then minimized.

The NXP single chip has multiple blocks like: tuner, digital processing, ADC, DAC, processor unit. Package effects are also modeled including inductance. Use cases are analyzed to find out which cases create the maximum digital switching activity, then results saved in a VCD file. For each case the analysis tools show on the IC layout the location on the chip where each cell is switching. The Apache tool used for substrate analysis is called RedHawk-CSE, and it accepts input files like: tech file, netlist, GDS II layout, package model, substrate tech file, digital block models, VCD file. The tool output is noise maps and numerical results.

For noise analysis, you look at the worst case VCD file. The RedHawk Explorer tool will show you the power profile for all available cycles. Current profiles are created by the tool as a function of time. Noise currents are compared versus the specification across the time domain.

Actual silicon measurements were made for noise at RF frequencies and compared versus simulated, providing a good correlation. Running the Apache tool required up to 60GB of RAM for the noise analysis on this radio chip. Run times were measured in the hours time frame: Setup, power calculation, extraction, and dynamic analysis. More CPUs will reduce the overall run times.

Complex RF-CMOS ICs can use this methodology to measure and reduce substrate noise levels, silicon measurements correlate well with simulated values, this analysis will reduce design spins which save money and time.

Q: Was it a challenge to get the substrate tech file?
A: For TSMC we derived the tech file, however now you may download this encrypted tech file.

Related Webinar

There’s also a pre-recorded webinar from ANSYS coming up on June 25th, 2014:

  • How to Use RedHawk 2014 for Power Noise and Reliability Sign-off of FinFET Based Designs
    • Distributed Machine Processing (DMP)
    • Chip-Package Co-Analysis (RH-CPA)
    • Temperature-aware EM methodology

Register for the webinar here.

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