Ansys addresses complex Multiphysics simulation and analysis tasks, from device to chip to package and system. When I was at eSilicon we did a lot of work on 2.5D packaging and I can tell you tools from Ansys were a critical enabler to get the chip, package and system to all work correctly.
Ansys recently published an Application Brief on how they address analysis of power management ICs. The tool highlighted is Ansys Totem, a foundry-certified transistor-level power noise and reliability platform for power integrity analysis on analog mixed-signal IP and full custom designs. I had the opportunity to speak with Karthik Srinivasan, Sr. Corporate Application Engineer Manager, Analog & Mixed Signal and Marc Swinnen, Director of Product Marketing at Ansys.
I began by probing the genealogy of Totem. Did it come from an acquisition? Interestingly, Totem is a completely organic tool that builds on the Multiphysics platform at Ansys that powers other tools such as the popular Ansys Redhawk. Organic development like this is noteworthy – it speaks to the breadth and depth of the underlying infrastructure. As Totem is a transistor-level tool, it delivers Spice-like accuracy according to the Application Brief. I probed this a bit with Karthik. Was Totem actually running Spice, and if so, how do you get an answer for a large network in less than geologic time?
Totem changes the modeling paradigm for the network to deliver results much faster than traditional Spice. All non-linear elements are converted to a linear model. All transistors are modeled as current sources and capacitors. These models are then connected to the parasitic network of the power grid. An IR-drop and electromigration analysis is then performed. This cuts the computational complexity of the problem down quite a bit. Totem provides targeted accuracy for the analysis of interest, typically within 5-10 mV of Spice, even for advanced technology nodes.
We discussed other applications of this approach. Power management ICs contain very wide power rails to handle the large currents involved in their operation. These structures are typically analyzed with a finite element solver, resulting in very long run times, typically multiple days. Using the Totem approach, a result with similar accuracy can typically be delivered 5-6X faster.
Using the Ansys Multiphysics platform, analysis can be performed from transistor and cell library level all the way to the system level. One platform, one source of models. IP vendors are also developing and delivering Totem macro models along with the IP to facilitate this kind of multi-level analysis. Marc pointed out that custom macro models are a key enabling technology to support this kind of transistor to system analysis. One first does the detailed analysis in Totem and then creates a macro model of the result to drive Redhawk.
The Ansys Application Brief goes into a lot more detail about the analysis capabilities of Totem. You can access the Application Brief here. To whet your appetite, here are some of the topics covered:
- Advanced Analysis: Power FETs, RDSON & sensitivity, guard ring weakness checks, transient power
- Early Analysis: device R maps, interconnect R maps, guard ring weakness maps
- PDN Noise Sign-Off: power, DvD, substrate noise
With DAC approaching, you can visit the Ansys virtual booth. Registration for DAC can be found here. There’s more to see from Ansys at DAC. The company has an incredible 25 papers accepted in the designer track (that’s not a misprint). Four of them focus on Totem. I also hear that Ansys is planning a special semiconductor-focused virtual event in the Fall. Watch your inbox and SemiWiki for more information on that as it becomes available.
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