WP_Term Object
(
    [term_id] => 34
    [name] => ANSYS, Inc.
    [slug] => ansys-inc
    [term_group] => 0
    [term_taxonomy_id] => 34
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 179
    [filter] => raw
    [cat_ID] => 34
    [category_count] => 179
    [category_description] => 
    [cat_name] => ANSYS, Inc.
    [category_nicename] => ansys-inc
    [category_parent] => 157
    [is_post] => 1
)

TSMC Theater Presentation: Apache

TSMC Theater Presentation: Apache
by Paul McLellan on 06-25-2012 at 12:13 am

At the TSMC Theater Apache (don’t forget, now a subsidary of Ansys) talked about Emerging Challenges for Power, Signal and Reliability Verification on 3D-IC and Silicon Interposer Designs. The more I see about the costs and challenges of 20/22nm and below, the more I think that these 3D and 2.5D approaches are going to be one of the main ways that we keep on the Moore’s law curve at the system level.

There are lots of challenges for 3D designs:

  • multi-die floorplan and place & route
  • manufacturing test
  • TSV-aware physical verification
  • TSV extraction
  • Power integrity
  • Reliability integrity
  • Signal integrtity
  • Wide I/O jitter analysis

Of course Apache is not directly involved in all of these, just the last 4. Apache have proactively been working with TSMC on these issues both for regular 20nm designs and for 3D designs.

 One of the most recent changes is the addition of more complete thermal analysis. This is then fed back into the power analysis (because high temperature affects performance which affects power which affects temperature…, not to mention it accelerates metal migration and other reliability issues). RedHawk is used to generate the Chip Thermal Model (CTM) which is fed into Sentinel-TI also with input from IcePick system thermal tools (to analyze heat flow out of the package etc). This combination makes very accurate thermal analysis, and thus the way that this effects performance ane reliability.

 Apache/ANSYS have been working closely with TSMC for 3D designs that combine power analysis from Apache with TSMC’s DFM Data-Kit (DDK) modeling to arrive at a complete analysis of a stack of die on an interposer in a package with heatsinks, in-package slugs etc.

One specific problem in the short term is analyzing Wide I/O since JEDEC has standardized wide I/O for memories meaning that there are lots of signal integrity issues, especially using Wide I/O on silicon interposer (where there is lots of routing involved too). The same problems arise with any wide bus, and wide-buses are common on 3D and interposer designs since the ability to have almost as many “pins” as you want is one of the advantages of 3D/2.5D.