The Silent Revolution is Underway, and Semifore is at its Epicenter

The Silent Revolution is Underway, and Semifore is at its Epicenter
by Mike Gianfagna on 07-21-2022 at 10:00 am

The Silent Revolution is Underway and Semifore is at its Epicenter

There is a major shift in innovation occurring all around us. We see the results every day.  We can interact with them in an easier, more intuitive way. They deliver insights about our health and our daily habits. All this can be categorized as a move towards Smart Everything – ubiquitous machine-assisted intelligence for the good… Read More


Upcoming Webinar: 3DIC Design from Concept to Silicon

Upcoming Webinar: 3DIC Design from Concept to Silicon
by Kalar Rajendiran on 01-26-2022 at 10:00 am

Lessons from Existing Multi Die Solutions

Multi-die design is not a new concept. It has been around for a long time and has evolved from 2D level integration on to 2.5D and then to full 3D level implementations. Multiple driving forces have led to this progression.  Whether the forces are driven by market needs, product needs, manufacturing technology availability or EDA… Read More


3DIC Design, Implementation, and (especially) Test

3DIC Design, Implementation, and (especially) Test
by Tom Dillinger on 12-20-2020 at 8:00 am

IO cell

The introduction of direct die-to-die bonding technology into high volume production has the potential to substantially affect the evolution of the microelectronics industry.  The concerns relative to the “end of Moore’s Law”, the diminishing returns of continued (monolithic) CMOS process scaling, and the disruptive effect… Read More


Design Considerations for 3DICs

Design Considerations for 3DICs
by Tom Dillinger on 12-14-2020 at 6:00 am

LVS flow phases

The introduction of heterogeneous 3DIC packaging technology offers the opportunity for significant increases in circuit density and performance, with corresponding reductions in package footprint.  Yet, the implementation of a complex 3DIC product requires a considerable investment in methodology development for all… Read More


Anirudh CadenceLIVE Plays Up Computational Software

Anirudh CadenceLIVE Plays Up Computational Software
by Bernard Murphy on 09-17-2020 at 6:00 am

Anirudh min

Cadence has clearly found its groove with Intelligent System Design, something that Lip-Bu reinforced in the CadenceLIVE kickoff keynote on Tuesday, August 11th. Anirudh Devgan, president of Cadence, continued to discuss the theme in his keynote on Wednesday, August 12th with his equally consistent subtitle—”Strength… Read More


A Quick TSMC 2019 Tech Symposium Overview

A Quick TSMC 2019 Tech Symposium Overview
by Daniel Nenni on 04-26-2019 at 7:00 am

This year TSMC did a FinFET victory lap with the success of 16nm, 12nm, 10nm, and 7nm. It really is well deserved. Even though TSMC credits the ecosystem and customers, I credit TSMC and their relationship with Apple since it has pushed us all much harder than ever before. TSMC CEO C.C. Wei summed it up nicely in his keynote: Innovation,… Read More


Power Integrity from 3DIC to Board

Power Integrity from 3DIC to Board
by Bernard Murphy on 09-14-2017 at 7:00 am

The semiconductor industry has built decades of success on hyper-integration to increase functionality and performance while also reducing system cost. But the standard way to do this, to jam more and more functionality onto a single die, breaks down when some of the functions you want to integrate are built in different processes.… Read More


The Death of Moore’s Law

The Death of Moore’s Law
by Michael Barger on 01-22-2016 at 12:00 pm

For the last several years, people have predicted the end of Moore’s Law. The reasoning is that there is a limit at which one can’t shrink transistors any further. A reoccurring comment has been “You can’t divide an atom.” I had assumed that its demise would be at the hands of a new paradigm like quantum computing. Now, with Intel’s … Read More


TSMC 10nm Readiness and 3DIC

TSMC 10nm Readiness and 3DIC
by Paul McLellan on 05-03-2015 at 1:00 am

At the TSMC Technology Symposium last month Suk Lee presented a lot of information on design enablement. Suk is an interesting guy with a unique background in ASIC, Semiconductor, EDA, and now Foundry. In baseball terms that would be like playing infield, outfield, home plate, and umpire!

Around the turn of the millennium Suk actually… Read More


TSV Modeling Key for Next Generation SOC Module Performance

TSV Modeling Key for Next Generation SOC Module Performance
by Tom Simon on 04-20-2015 at 1:00 pm

The use of silicon interposers is growing. Several years ago Xilinx broke new ground by employing interposers in their Virtex®-7 H580T FPGA. Last August Samsung announced what they say is the first DDR4 module to use 3D TSV’s for enterprise servers. Their 64GB double data rate-4 modules will be used for high end computing where … Read More