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DesignSync update from Dassault Systems at DAC

DesignSync update from Dassault Systems at DAC
by Daniel Payne on 06-24-2012 at 8:10 pm

At DAC on Wednesday Rick Stanton of Dassault Systems gave me an update on what’s new with DesignSync, a design data management tool offered since 1998. Rick and I both worked at Viewlogic in the 90’s along with Dennis Harmon who then founded Synchronicity, later acquired by Dassault Systems.

What’s new in 2012?
Whole product development is captured with Dassault, specification, requirements, optimize design process, prepare for manufacturing, simluate each step.

DesignSync is the most popular tool we are known for. We have accounts with 4,000 users in production.

Recent features: Graphical Diff tool in the Virtuoso environment (5.1 and later releases).

Cadence Connections, Synopsys inSync (not Mentor, but they did integrate Visual HDL tools and IC Station at one time themselves), SpringSoft wrote their own integration.

ST, Freescale, TI – all deploy DesignSync and employ Enovia PLM tool for Product Lifecycle Management (competes with Oracle, IBM, etc).

New feature – hierarchical defect management to leverage module capability (abstract data), abstract an IP block into change sets and connect them hierarchically, traverse info up and down the chain. Find a bug in one IP block, then what other projects use that same IP block to manage the impact of changing it.

Track bugs and issues up to the enterprise level as well. File a bug or defect report, then include multiple child defects, then actions can be assigned to multiple team members. Bugs get closed as reviewed and fixed, wait until all actions and child issues are resolved. If ECOs come in then how does that impact my chip or system?

CAPA – Corrective Action Preventive Action, find problem and ensure it never happens again. Compliancy rules can dictate how thorough your product is designed and documented.

DesignSync – we think our market share is #1 in the world.

Pricing – not public, ask for a sales quote.

Evaluation of DesignSync – set up the criteria first, train users on how to use the tool, most evaluations take a few weeks.

Trends – moving away from simple file management to more abstractions.

SITAR – Submit, Integrate, Test and Release. It’s our methodology or use model built into DesignSync.

For IP development how to manage and test all of the releases? With SITaR we can help automate that process. Testing can be done against the current or new baselines, eliminating errors. Works with PDK release process.

Moving DesignSync more and more into SW development by integrating with Eclipse and MS Visual Studio.

Finite Element Analysis –

SImulation Lifecyle Management (SLM) – big in other industries that helps tie into other simulation tools, like Visio or Synopsys Lynx. You can tie together various EDA vendor tools into a single, automated flow.

What would success look like in 12 months?
I would like to see Modules get more of a mainstream adoption. Moving more into tools for embedded SW developers. Want to bring more collaboration between embedded SW and HW developers.

Product Data Management – it’s more than just check in and check out, SW would never start without it, so chip designers are just catching up to that discipline.

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