The electronic design community is well aware that it faces a daunting challenge to analyze and sign off the next generation of huge multi-die 3D-IC systems. Most of today’s EDA tools require extraordinary resources in specialized computers with terabytes of RAM and hundreds of processors. Customers don’t want to keep buying… Read More
On the eve of the Innovative Designs Enabled by Ansys Semiconductor (IDEAS) Forum I spoke with Vic on a range of topics including his opening keynote: Accelerating Moore and Beyond Moore with Multiphysics. You can register here.
Vic Kulkarni is Vice President and Chief Strategist, Semiconductor Business Unit, Ansys, San Jose.… Read More
Tue, Mar 31, 2020 11:00 AM – 12:00 PM MDT
*** This webinar requires that you register with your work email address ***
As we move towards advanced nodes where supply voltage reduces and transistors shrink in size, reliability challenges increase significantly. Designers see more IR drop and power integrity issues, and we… Read More
March 30, 2020 – March 31, 2020
9:30 AM – 4:30 PM (PDT)
Venue:
ANSYS, Inc.
2645 Zanker Road
San Jose, CA 95134
USA
Contact:
Phoebe Lee
Join us for a free 2-day hands-on workshop where you will learn how to perform on chip static and dynamic voltage drop analysis, electromigration, design weakness… Read More
March 23, 2020
9:30 AM – 4:30 PM (PDT)
Venue:
ANSYS, Inc.
2645 Zanker Road
San Jose, CA 95134
USA
Contact:
Phoebe Lee
Join us for a free hands-on workshop to learn how to perform on chip static and dynamic voltage drop analysis, electromigration, design weakness and hot spot analysis using ANSYS RedHawk.… Read More
Advanced IC technologies, 5nm and 7nm FinFET design and stacked packaging, are enabling massive levels of integration of super-fast circuits. These in turn enable much of the exciting new technology we hear so much about: mobile gaming and ultra-high definition mobile video through enhanced mobile broadband in 5G, which requires… Read More
Designing with advanced-nodes FinFETs such as 7nm node involves a more complex process than prior nodes. As secondary physical effects are no longer negligible, the traditional margin-based approach applied at various design abstraction levels is considered ineffective. Coupled with the increase of device counts, failing… Read More
There’s a familiar saying that you can’t improve what you can’t measure. Taking that one step further, the more improvement you want, the more accurately you have to measure. This become pretty important when you’re building huge designs in advanced technologies. Margins are a lot tighter all round and use-cases are massively… Read More
There is a nice serendipity in discovering that two companies I cover are working together. Good for them naturally but makes my job easier because I already have a good idea about the benefits of the partnership. Synopsys and ANSYS announced a collaboration at DAC 2017 for accelerating design optimization for HPS, mobile and automotive.… Read More
I’m not going to be at DAC this year because I scheduled a fishing trip at the end of June, assuming the show would stay true to form as an early/mid-June event. Still, having to endure salmon and halibut fishing in Alaska rather than slogging around Moscone Center, I can’t pretend to be too disappointed; I’ll be thinking of you all 😎.… Read More
