Advanced IC technologies, 5nm and 7nm FinFET design and stacked packaging, are enabling massive levels of integration of super-fast circuits. These in turn enable much of the exciting new technology we hear so much about: mobile gaming and ultra-high definition mobile video through enhanced mobile broadband in 5G, which requires support for millimeter wave frequencies; high-speed networking in hyperscalar datacenters through 100G connectivity; blazing fast AI accelerators in those same datacenters; and fusion of multiple sensor sources to build environment-aware intelligence for automotive safety and autonomy, building security, autonomous drones and many more capabilities.
With new technologies we always find new challenges. ANSYS and others have been hearing from chip and system builders supporting these domains that they are seeing increasing post-silicon failures in the devices they are building. These devices are nominally perfectly fine, pass standard testing, but fail in system operation primarily related to voltage, timing and process variations. Tianhao Zhang (Dir. Foundry Relations at ANSYS) says that between what they are hearing from customers and industry reviews, 75% of these product failures can be attributed to thermal or vibration effects.
Thermal also increases cost through need for more advanced cooling, it reduces performance through increased resistance in the interconnect and degraded transistor performance and it increases noise leading to random failures. It also decreases reliability, on chip through electromigration and device aging, and in the package and system through mechanical stress during to warping.
This is not a problem that can be dealt with later. One chip design VP has said that self-heating (related to FinFETs) and thermal analysis are now absolute requirements for automotive and high-performance computing applications. Another noted that compared to planar designs they are now seeing temperature increases in metal of 10 to 20 degrees, and that is making design for reliability much more challenging.
TSMC has been hearing all the same issues and has been increasing the number of checks they require, particularly thermal checks, to offset these types of problem. TSMC has worked closely with ANSYS to prove and document a thermal solution they jointly support. This includes an ANSYS reference flow for transistor, chip and package/3D-IC levels, from 20nm down to 5nm. These can be downloaded from the TSMC portal.
They are also working together on solution guides for specific application flows. For example, ANSYS now provides solution guides for automotive development on 16nm and 7nm. These cover electromigration, thermal and ESD topics. In the thermal analysis section, the document details multiple areas including the flow, and also provides test cases and case studies.
The ANSYS analysis is not based on a simple averaging of thermal effects. They analyze all the way down to the physical implementation of transistors and interconnect systems under representative activity scenarios, to estimate local heating, interconnect heating and heat dissipation. They do this using analytics from RedHawk, together with finite-element analysis applied at the die, stacked die, package and board level. And they’re computing temperature profile by looking at (thermal) conduction, radiation and convection flows, the last of these though detailed fluidics analysis. This is a true bottoms-up multi-physics solution. You can learn more in THIS WEBINAR, presented by Tianhao and Karthik Srinivasan (Sr Prod Mgr at ANSYS).