I’m not going to be at DAC this year because I scheduled a fishing trip at the end of June, assuming the show would stay true to form as an early/mid-June event. Still, having to endure salmon and halibut fishing in Alaska rather than slogging around Moscone Center, I can’t pretend to be too disappointed; I’ll be thinking of you all 😎.
One of the things I’ll miss is the ANSYS update on status which, from the information I have, is shaping up to be quite impressive. DAC has accepted 25 ANSYS-related customer papers/posters from all major geographies. Among these the majority seem to come from the who’s who of mobile, while the majority of topics are RedHawk-SC (the big-data version), RedHawk for 3DIC/InFO/CPM and PathFinder (ESD analysis). Good to see these technologies, about which I have been writing for a while, are both trending and translating into successes. (I confess I haven’t seen the papers but I’m assuming no-one wants to brag about failures.)
Vic Kulkarni (VP and Chief Strategist in ANSYS SCBU) gave me a rundown on their theme and events for DAC. The headline is “Beyond Signoff”, getting past traditional margin-constrained analyses to more effective approaches. I wrote about this earlier (breaking out of the box) on my John Lee interview. They’ll be highlighting applications in four main areas:
- Mobile – a lot of innovation still, even though the smartphone market is flattening out (think 5G, basestations, AI, 3D-sensing, …). A lot of activity in advanced packaging.
- High-performance computing (HPC) – CPUs and GPUs of course but also networking and crypto-currency (I learned the in-term for this is now simply crypto. I guess the encryption folks lost that tag.). Advanced packaging big here too.
- 5G/AI – an odd pairing from a solution point of view but it seems both are pushing ultra-high performance, power and reliability hard. Advanced packaging is also big here.
- And of course, automotive – where pretty much everything is critically important, use of advanced processes is becoming more common and there are some moves into advanced packaging, if not quite as aggressive (yet) as in other domains.
The ANSYS story across all these domains remains very consistent – the margin-based approach to design and signoff is breaking down, a point on which I have written multiple times. You don’t have to be a semiconductor expert to understand this. In any type of engineering, the standard way to study the characteristics of a design is vary one thing at a time and hold everything else constant, because we haven’t known how to analyze with everything varying at the same time. We make allowance for variability in other factors through margins – limits on how much each factor can vary, and we repeat analysis at combinations of those extreme cases (the corners).
This approach works fine in many cases, but obviously it is a simplification of a more complex problem. It’s not hard to imagine circumstances under which that simplification would break down, particularly where there may be strong coupling between different factors. In mechanical engineering this happened quite a while ago. Aircraft-engine design requires co-analysis of mechanical, heat and airflow at the same time because analyzing these independently is already known to be dangerously inaccurate. FYI, this co-analysis across multiple domains is commonly known as multi-physics analysis.
Semiconductor design is no different. The question is not if but when co-analysis becomes important in this domain. Perhaps we are so far away from those kinds of interdependency that we can comfortably continue to use our margin-based approaches? Customers using advanced processes and packaging appear to disagree. They’re saying they have to look at multiple factors at the same time, and if they don’t they lose pricing advantage, PPA, yield and even reliability. But I admit I get my information though ANSYS and I’m a sucker for reasonable physics explanations, so you should probably sit in on some of the customer papers at DAC to form your own opinion.
You’ll have multiple chances at DAC to pick apart the story. ANSYS have four customer workshops: design for optimal PPA, early power analysis for IP and chips, accelerating SoC power signoff and multi-physics reliability signoff. They have seven best practices sessions, John Lee (GM) is speaking at a Synopsys special interest group dinner, Norman Chang (CTO) is speaking at an AI/ML workshop and there will be customer presentations at the booth. You can learn more and signup for events HERE. I’ll tell you what I caught when I get back and you can tell me what you thought of the ANSYS story.Share this post via: