WP_Term Object
    [term_id] => 34
    [name] => ANSYS, Inc.
    [slug] => ansys-inc
    [term_group] => 0
    [term_taxonomy_id] => 34
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 179
    [filter] => raw
    [cat_ID] => 34
    [category_count] => 179
    [category_description] => 
    [cat_name] => ANSYS, Inc.
    [category_nicename] => ansys-inc
    [category_parent] => 157
    [is_post] => 1

ANSYS Updates RedHawk for FinFET Nodes

ANSYS Updates RedHawk for FinFET Nodes
by Tom Simon on 12-30-2014 at 7:00 am

Most designers are not using FinFETs yet, however the increased transistor density and power advantages they offer are compelling. Smaller feature sizes have been a consistent driver in semiconductor technology. Eventually the market will move more and more to FinFET processes, increasingly leaving behind planar transistors. Nevertheless, today FinFETs are used on high end designs, and this means that fabs and designers are working through all the new issues that come with them. There is the need for additional lower level local routing layers. New models, such as BSIM-CMG, are required to get accurate simulation results. Lithography is changing as well. And there are a number of other new issues and challenges.

Sign off for power, noise and reliability are going to change with FinFETs. A recent white paper by ANSYS highlights how each of these areas will need to change. The paper is titled “System-Aware SOC Power, Noise and Reliability Sign-off” and can be found by going to this page. I have always felt that ANSYS (formerly Apache) took hard-to-solve but important problems and built unique solutions for designers. This white paper does a good job of articulating the problems and solutions for advanced node FinFET dynamic voltage drop and the related issues of ESD and electromigration analysis. I used to work for Sequence Design, later acquired by Apache prior to their merger with ANSYS. Back then work started on a comprehensive voltage drop solution. With that early work in combination with Apache technology, ANSYS now has a very impressive solution that has been extended with RedHawk 2014 to address FinFET based designs.

To properly address voltage drop, a full and accurate model of switching activity across the whole chip is needed. Using ANSYS RedHawk this can be done with simulation output from a FSDB file or other sources. Or, this can be accomplished earlier in the design flow before good simulation results are available by using RedHawk’s VectorLess™ dynamic simulation engine. RedHawk supports multiple modes for running VectorLess™; they are PowerTransient™, FrequencyAware™ and VectorLess Scan™. RedHawk can mix gate level simulation data with RTL simulation data to get an accurate view of activity when some blocks have not yet been run at gate level. The white paper stresses that the important elements are to simulate the switching at the full chip level, which should include instance specific block level switching activity, and to include package and even board level power supply models.

To decrease dynamic power these chips use lower voltages. This comes at the expense of a lower noise margin. FinFET devices have higher drive strengths, which translates into more dynamic switching strain on the power supply network accompanied by greater thermal dissipation issues from self heating. Higher current on smaller wires also exacerbates electro-migration (EM). One of RedHawk’s advantages appears to be that it accurately models self heating effects and avoids having to apply worst case self heating data during EM analysis. The following figure illustrates this.

The RedHawk white paper discusses how distributed multi-processing is used to make it feasible to run a full chip analysis, with minimal loss in accuracy. Taking things one step further, the while paper talks about how RedHawk supports stacked die designs and can model TSVs used with interposers. The different dies can even be built with different process nodes. Package structures such as micro bumps and copper pillars are included in the RedHawk analysis.

To meet low power requirements, a high performance SOC might have multiple supply voltages, dozens of power islands, and multiple clock domains. Power gating and clock gating also affect dynamic voltage drop. These design approaches further complicate validation of power grid performance due to dynamic loads and different operational modes of the chip. The white paper discusses how RedHawk deals with these complicating factors in those designs.

Lastly the white paper touches on enhancements to the GUI for RedHawk. There is support for multi-pane views to aid in visualizing and debugging design issues. RedHawk includes the RedHawk Explorer (RHE) that designers can use to locate problems so they can be fixed. It should be useful in locating root causes of power integrity issues.

Based on this white paper it looks like ANSYS is doing an excellent job of keeping up with innovations in the semiconductor design process. At this juncture it is important that they continue to deliver as they bring the Apache tool set under the umbrella of the ANSYS multi physics tools, such as HFSS™, Icepak™ and SIwave™.

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