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New Vivado Release. And a Competition!

New Vivado Release. And a Competition!
by Paul McLellan on 12-29-2014 at 5:00 pm

 It is not entirely clear what Xilinx is these days. Of course it is an FPGA company. If you hear the word FPGA then I bet Xilinx is the first thing you think of. But what Xilinx ships these days is a far cry from the type of device it created when it was starting, where FPGAs were largely used to vacuum up all the glue logic around the processors and memories on a circuit board. Back in those days a microprocessor was a whole chip and it wasn’t possible to embed one. Now an entire system can be implemented in a Xilinx part. But one key part of the whole system is the Xilinx software toolchain Vivado that is used to program the devices, often starting from Verilog or VHDL but increasingly from C/C++, especially when the person writing the code is actually a software engineer with no (or limited) hardware design experience. As the design of systems moves to the higher level, increasingly the design is being done by engineers who do not know RTL.

Xilinx has just announced a suite of new capabilities in the software with the release of Vivado 2014.4. This release adds support for many of the 28nm and Ultrascale devices in particular the Artix-7 and Zynq-7000 including the recently announced low power/speed grades. The full table of supported devices is above.

More information on Vivado is here.

See also Xilinx Announces SDAccel, Accelerators for the Datacenter

Another feature is the partial reconfiguration capability. I wrote about this earlier in the context of the SDAccel. Partial reconfiguration allows the array to be partially reprogrammed without requiring the entire bitstream to be reloaded. Indeed, the part of the array not being reprogrammed can continue to operate at the same time, allowing a large array to be dynamically loaded with whatever functionality is required at that time.

Peeling back one more layer of the onion, partial reconfiguration allows for the dynamic change of modules within an active design. This flow requires the implementation of multiple configurations which ultimately results in full bitstreams for each configuration, and partial bitstreams for each Reconfigurable Module. The number of configurations required varies by the number of modules that need to be implemented. However, all configurations use the same top-level, or static, placement and routing results. These static results are exported from the initial configuration, and imported by all subsequent configurations using checkpoints.

More information on partial reconfiguration is here.

It is also time for the Vivado Design Leadership Awards. There are two categories:

  • All programmable design leadership focusing on designs using Xilinx FPGAs and 3D ICs
  • Smarter systems design leadership focusing on designs using Xilinx Zynq-7000 all-programmable SoCs, hardware and software programmable devices enabling rapid design and implementation of smarter systems

As Xilinx themselves say:
We are looking for the best of the best. To enter, applicants should submit their design in technical paper format. The winners will be honored with public recognition via a press release, promotion within Xcell Publications, a glass design leadership award for the winners, an award plaque prominently displayed at Xilinx Headquarters in San Jose, California and the opportunity to present the winning technical paper at the Club Vivado Users Group 2015.

To enter go here.

More articles by Paul McLellan…

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