What do nVidia, Freescale and GlobalFoundries have in common? They are semiconductor companies? They are ARM licensees? They are doing 28nm chips? They all have the letter ‘a’ in their names?
All true, but that’s not what I was thinking of. But the letter ‘a’ is a clue since Apache (and Ansys) begin with ‘a’. All three companies have issues with various aspects of semiconductor power that they look to Apache to help them address. Is there anyone designing chips who doesn’t have issues with power? Of course not. Which means that everyone would benefit from another connection, that in the next few weeks they are all doing Apache webinars about power, noise, power reduction, reliability, and power delivery network analysis.
Apache, a subsidiary of Ansys in case you’ve forgotten, is the de facto standard for pretty much anything in the power area, from high-level early analysis at the RTL level down to the most accurate post-physical-design analysis of the entire power network from board, through the package and onto the chip.
All three customers presented at the Apache booth during DAC a few weeks ago. But if you couldn’t make it to Austin then you can see what you missed (although I don’t think you’ll get a cute toy dog).
First up is nVidia on July 16[SUP]th[/SUP] at 10am Pacific talking about Early RTL Power Analysis and Reduction for Advanced Power-Efficient GPU Designs. This webinar covers nVida’s methodology for RTL power analysis and reduction using PowerArtist. Material presented will include RTL vs sign-off power correlation, runtime performance metrics, and specific examples of power reduction techniques applied and results achieved. Register here.
Next is Freescale on July 23[SUP]rd[/SUP] at 10am Pacific on Power, Noise and Reliability for Advanced Automotive and Networking ICs. This webinar covers experiences of SoCs for Automotive and Networking Applications. Instead of discussing typical Power and Rail Analysis details, this presentation will focus on insights gathered from running analysis and silicon results, and will include power analysis (RTL and gate-level), rail analysis (static and dynamic), handling complicated IPs and standard cells, ESD signoff and cell electromigration analysis. Register here.
And on August 6[SUP]th[/SUP] at 10am Pacific, GlobalFoundries will talk on Hierarchical Voltage Drop Analysis for Complex Power-Gated, Multi-Domain 20nm Designs. This webinar will cover a hierarchical IR drop analysis flow using Totem to trace networks of over 800 multi power domains through switch cells, and to generate sub-block abstracts that can be used for top-level analysis, allowing a large speed-up of IR drop analysis in comparison to flat analysis. Registerhere.
More details of the webinars including links for registration are on the Apache website here.
DAC news: The ACM/IEEE A.R.Newton Technical Impact Award in EDAwas awarded to Keith Nabors of Apache, who co-authored (along with Keith White) the paper FastCap: a Multipole Accelerated 3D Capacitance Extraction Program. He received the award at the DAC 50[SUP]th[/SUP] Awards Dinner on the Wednesday evening of DAC. The paper was picked because of its impact on the industry but Keith probably had a hard time remembering much about it since it was published over 20 years ago when he was at MIT. If you want to read the paper it is here.Share this post via: