Sanjay Lall, Sam Appleton – Ausdia
Q: Who uses your EDA tools?
Who: RTL designers and chip integrators, before it gets handed off to physical implementation.
Language: Verilog, SystemVerilog, VHDL, mixed-languages.
Q: What do your tools do?
What: SDC (Synopsys Design Constraints) verification, timing constraint generations, to handoff to backend guys, find errors in spec before physical.
Q: How similar to Fishtail?
Closest competitior. We are 20 to 50x faster than Fishtail, capacity of millions of gates (2.5 B flat gates).
Verification purpose of SDC.
For full chip, it’s just verification.
Q: How new is your TimeVision tool?
Started development in 2008, production in 2010, 2012 closed first tier one account, two more tier one accounts, another 5 (top 20 semi companies).
Q: How long does it take to learn your tool?
Learning curve – AE installs it, we are competent in a month. Another month or so to make final decision.
Q: How do I use TimeVision in my design team?
Multiple copies per team used, and 1-2 copies per engineer. Term based license, 1 2 3 year leases.
Q: Are you part of any 3rd party programs?
Yes, Mentor OpenDoor program – On DFT side, they are dominant.
– Cadence, some interest.
Q: How large is your company?
Ausdia – 14 people, R&D in Sunnyvale. Some from Austin.
Sam – PhD in Australia, worked at Silicon Graphics, start ups, did own start up.
Q: How is your company financed?
Ou company – privately financed.
Q: What should I expect to see in the next year from Ausdia?
By 2014 – have 1/2 of the world’s top 10 semi companies. Two new products. Grown substantiality.
Q: Who do I call for an evaluation?
Evaluate – Call the factory in USA.
Q: What have you learned at DAC this year?
DAC lessons – Customers are needing CDC, designs are getting too complex. Good to see Austin customers.
Q: What other EDA companies do you partner with?
Partners – DFT verification (Defacto), Design Management vendors (Methodics, IC Manage)
Q: Are you product protected by patents?
Patents – First one issued, four more applied for.
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