CadenceTECHTALK: Low-Power Verification Using Xcelium Simulation

CadenceTECHTALK: Low-Power Verification Using Xcelium Simulation
by Admin on 01-16-2023 at 2:09 pm

Don’t let power-related issues that appear late in the verification cycle impact your project schedule. Register for a webinar that shows you how to catch low-power issues early on.

The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation,… Read More


Slashing Power in Wearables. The Next Step

Slashing Power in Wearables. The Next Step
by Bernard Murphy on 11-02-2022 at 6:00 am

Fitness bamd and phone min

In wearables and hearables, low power is king. Earbuds for example still only manage a half-day active use before we need to recharge. Half a day falls short of truly convenient for most of us – a full day would be much better, allowing for overnight recharge. Physics limits battery sizes so system designers must look to SoC architectures… Read More


Cadence TECHTALK: Low-Power Verification using Xcelium Simulation

Cadence TECHTALK: Low-Power Verification using Xcelium Simulation
by Admin on 10-19-2022 at 2:12 pm

Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel / 13:30 IST

The Cadence low-power solution considers power at every step of the design flow, from architecture to functional verification, analysis, implementation, and signoff. In this webinar, the focus will be on the functional verification of the RTL with the power intent

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CadenceTECHTALK: Driving Low-Power Design with High-Level Synthesis

CadenceTECHTALK: Driving Low-Power Design with High-Level Synthesis
by Admin on 09-15-2022 at 1:29 pm

Date: Wednesday, October 12, 2022

Time: 09:00 BST / 10:00 CEST / 11:00 EEST and Israel

With the growth in computing at the edge driven by the explosion in the number of battery-powered smart devices, designing for low power is mission-critical to product success. Numerous techniques, spanning all stages of design, are employed

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Driving Low-Power Design with High-Level Synthesis

Driving Low-Power Design with High-Level Synthesis
by Admin on 06-22-2022 at 1:42 pm

With the growth in computing at the edge driven by the explosion of battery-powered smart devices, designing for low power is mission-critical to product success. Numerous techniques, spanning all stages of design, are employed to reduce power. Since many of the low-power design techniques come at a cost in performance, the … Read More


The Importance of Low Power for NAND Flash Storage

The Importance of Low Power for NAND Flash Storage
by Tom Simon on 04-05-2022 at 10:00 am

Low Power for NAND Flash

Even though we all know that reducing power consumption in NAND Flash Storage is a good idea, it is worthwhile to take a deeper dive into the underlying reasons for this. A white paper by Hyperstone, a leading developer of Flash controllers, discusses these topics providing useful insight into the problem and its solutions. The … Read More


It’s Now Time for Smart Clock Networks

It’s Now Time for Smart Clock Networks
by Tom Simon on 01-13-2022 at 10:00 am

Movellus Maestro Clock Network

By now most SoC designers are pretty familiar and comfortable with the use of Network on Chip (NOC) IP for interconnecting functional blocks. Looking at the underlying change that NOCs represent, we see the use of IP to supplant the use of tools for implementing a critical part of the design. The idea that ‘smart’ things are better… Read More


Low Energy SoCs with Near Threshold Voltage

Low Energy SoCs with Near Threshold Voltage
by Tom Simon on 04-15-2021 at 6:00 am

Low Energy Efficiency

There is an important difference between low power and low energy in SOC design. Low power focuses on instantaneous power consumption. This is frequently done to deal with cooling and heat dissipation issues. Of course, it serves as a prerequisite for low energy design, which seeks to reduce overall power consumption over time.… Read More


Hearables: From Earbuds to Life Augmentation and Beyond

Hearables: From Earbuds to Life Augmentation and Beyond
by Kalar Rajendiran on 03-09-2021 at 10:00 am

Hearables Market Players Source IDTechEx Research

As the months of 2020 passed by, I started noticing more and more people sporting what looked like fashionable ear accessories. I’m of course referring to True Wireless Stereo (TWS) earbuds. With the rapid increase in online meetings due to social distancing requirements, it appeared that adoption of TWS earbuds was even faster… Read More


Probing UPF Dynamic Objects

Probing UPF Dynamic Objects
by Tom Simon on 01-28-2021 at 6:00 am

Probing UPF Dynamic Objects

UPF was created to go beyond what HDL can do for managing on-chip power. HDLs are agnostic when it comes to dealing with supply & ground connections, power domains, level shifters, retention and other power management related elements of SoCs. UPF fills the breach allowing designers to specify in detail what parts of the design… Read More