A few months ago, when the Xilinx UltraScale VU440 FPGA began shipping, one of the immediate claims was a quad-FPGA-based prototyping board touted as “Godzilla’s Butcher on Steroids”. That was a refreshing and creative PR approach, frankly. I’m always careful with less creative terms like “world’s biggest” or “world’s fastest”, because they can overstate a snapshot – such a claim can easily dissipate tomorrow. I prefer a term like “industry first” since it recognizes that.
If the news of four UltraScale parts on a board was big back then, Aldec’s announcement of six UltraScale VU440 parts on a single board is bigger. This is a major upgrade to the Aldec HES-7 12000 platform, supplanting the Xilinx Virtex-7 devices on it. In the previous configuration, four boards each with six Virtex-7 parts offered up to 288M gates.
This new UltraScale frontier for HES-7, coming in 3Q15, puts together four boards each with six UltraScale VU440s for a capacity of up to 633M gates. I do expect others to try to match the sheer capacity of this FPGA-based prototype offering soon, but for now, Aldec leads with an industry first.
Matching the rest of the Aldec HES-7 offering will be more challenging for its competitors. Aldec’s high speed backplane supports the interconnect needed to keep UltraScale parts running at their potential. Their HES-DVM automated partitioning capability leverages SCE-MI to help connect the physical FPGA hardware to software simulation features for more complete verification. Aldec offers a range of off-the-shelf daughtercards for HES-7, including a Xilinx Zynq-based board, along with support for FMC modules. They also offer custom design services for daughtercards, aiding in incorporating exact copies of hardware, crucial in safety-critical and DO-254 validation.
UltraScale parts introduce another aspect where Aldec has an industry leading solution: clock domain crossings (CDCs). The clock resources in UltraScale architecture have been completely redesigned. The good news is the design flexibility and ease of synthesis closure has been greatly increased. At the same time, the odds of CDCs occurring have also increased. Without mitigation, CDCs can cause unpredictable effects such as metastability and data incoherence. Aldec ALINT-PRO-CDC is geared to comprehensively find CDCs, examine synchronizer constructs, and flag issues for designers. This tool is handy for both FPGA designers and SoC teams using FPGA-based prototyping, since CDCs play no favorites – especially when doing manual partitioning.
In other words, Aldec is not just gluing constantly bigger parts on boards and calling it a day. They are assembling a complete set of capability for FPGA-based prototyping, from design to simulation to debug to verification to compliance, enabling more FPGA and SoC designers to get more done quickly and reliably. There is more of this story in the press release:
For those attending DAC 52 in fabulous San Francisco with exhibits starting June 8, Aldec will be offering eight technical sessions on a range of topics. Session 1 focuses on FPGA-based prototyping and the scalability UltraScale devices bring to HES-7 Ultra. Registration for these sessions is free to DAC exhibit attendees but first-come, first-served with limited seating, simply follow the online form linked above to reserve a spot.