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Ultra-Low Power Non-Volatile Memory Solutions for the Smart Connected Universe

Ultra-Low Power Non-Volatile Memory Solutions for the Smart Connected Universe
by Tom Simon on 06-01-2015 at 6:00 pm

DAC is a great place to gather information about products and technologies. However it can be difficult to chase down the information you need because you may need to cover a lot of ground to hear or talk to the people with the right knowledge. Fortunately there are a few places you can go to learn about a number of products at one place. A really good example of this is the Open Innovation Platform Theatre that is hosted by TSMC. Throughout this year’s DAC they will have speakers from their ecosystem partners giving short presentations on important topics.

One such presentation will be given by Sidense CTO Wlodek Kurjanowicz on the topic of Ultra-Low Power Non-Volatile Memory Solutions for the Smart Connected Universe. Sidense sees the combined market segments of mobile, IoT, medical, automotive and the cloud infrastructure needed to support them as a key areas for product development. Low power requirements are prevalent within this category. Durable non-volatile memory is needed for many purposes, including security codes, calibration trim information storage, device ID’s, secure boot code storage, etc. Having the ability to use standard CMOS processes and minimize power consumption are important success factors.

Sidense will also be presenting at the Chip Estimate booth on the more general topic of Memory Requirements in the Smart Connected Universe. As is usually the case I’m sure there will be a video of this presentation produced by Chip Estimate for viewing later. There are already videos concerning Sidense available at Chip Estimate. A lot of useful information about Sidense and their offerings can be found on that page, including recent additions to their process availability matrix.

However seeing the presentation in person and having the opportunity to speak directly with their technical experts is invaluable. Webinars and video conference calls are convenient and useful, but meeting people face to face can never really be replaced. Hopefully you can leave DAC with your questions answered and much more confident in a vendor’s ability to deliver critical elements for your projects.

In the case of Sidense, it is their IP that get incorporated into the finished product design. Understanding their foundry qualification process, design methodology, as well as interface & programming options by having them explained first hand would be hard to pass up if you are looking for a non volatile memory solution.

The TSMC OIP presentation will be offered on Monday 6/8 at 11:30 AM, Tuesday 6/9 at 3:15PM and Wednesday 6/10 at 2:00PM in booth #1933. The Chip Estimate presentation will be offered on Tuesday 6/9 at 2:30PM and Wednesday 6/10 at 1:30PM at booth #2433. For info on both presentations there is a link here.

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