When people think about non volatile memory, the first thing that usually comes to mind is NAND flash like that used in SSD’s or in microcontrollers to hold on-board code. Of course, there is also EEPROM and other types of NVM as well that can be used to hold data and code for the multitude of connected devices that are so common now. For many SOC designs NAND flash or EEPROM might be the go-to technology for re-writeable persistent storage. However, there are some down sides to this technology, and there is an attractive alternative worth considering. So, what might make SOC designers think twice about going with NAND flash?
I learned more about the specifics of this while I was at the TSMC Technology Symposium on March 15[SUP]th[/SUP]. I had the opportunity to have lunch with Ken Wagner, Sr. VP of Engineering, and Andrew Faulkner, Sr. Director of Marketing, at Sidense, provider of one time programmable (OTP) IP for integration into SOC’s.
The top drawback for considering adding NAND flash or many other NVM’s is that they require additional mask layers or special processes. These requirements cost more money, introduce risk and can limit options for fabrication. In many applications security and durability are essential. Technologies that use charge storage can be perturbed and suffer data loss. They are also vulnerable to thermal degradation. IoT devices and mobile devices can be subjected to intense environmental conditions. Another application where heat is a significant factor is in the automotive arena. Floating charge devices can be probed externally to reveal their contents. Side channel attacks can also sometimes decipher the contents of flash storage.
Nevertheless for frequent re-writes, flash memory is a good NVM option. Frequently in addition, SOC’s often include one time programmable (OTP) memory for storing parameters, data, or even code that do not change. If rare changes are needed, OTP can be configured as few-times programmable (FTP) so that field updates can be performed as a necessity.
As middle ground, Sidense offers what they call emulated multiple time programmable (eMTP) NVM. Sidense has cleverly implemented features in their RTL NVM controller, which is delivered as RTL, to automatically handle the remapping of the one time writable physical layer, into an emulated multiple write interface. The granularity of the re-write size and number of re-writes available are configured during SOC implementation.
Once the restrictions of extremely limited re-writes is lifted, the technology used to implement anti-fuse NVM starts to look extremely interesting. No extra mask layers are needed. It can be implemented on conventional planar MOS transistors or on FinFET’s. So, the range of available nodes is very large, right up to the latest TSMC offerings. The bits are physically encoded by irreversibly breaking down the gate oxide with tiny conductive holes. One benefit of this approach is that there is no method to physically observe the state of a bit cell due to the virtually atomic level of the write action.
Another advantage of the 1T-NVM bit cell is that it is extremely reliable. Sidense offers TDDB testing that assures 10-year memory retention of 100%. Their NVM is qualified for AEC-100Q Grade 0 and 1 automotive applications. Sidense’s 1T-NVM bit cell is very compact so there are area savings with this approach. An available on-board charge pump can eliminate the need for external power pins for the write operation. Write times are very short, offering another advantage over other technologies. The arrays they offer are large enough to give very high re-write counts for data and parameters, and numerous re-writes for code storage.
While, eMTP NVM is not suitable for all applications, it certainly offers an attractive solution in between OTP NVM and the alternative of having to change over to NAND flash with all the consequences. Sidense has much more detailed information available about emulated multiple times programmable non volatile memory on their website.