Have you ever had a peanut butter and bacon sandwich? Everything goes better with bacon! Which brings me to one of my favorite sayings: “(insert two complimentary things) go together like peanut butter and jelly”. How about this: “low power and IoT”, “IoT and OTP”, and “Low Power OTP and Sidense go together like peanut butter and jelly!”
Programmable memory started with PROMs in the 1950s and moved to antifuse one time programmable memory in the late 1960s. Texas Instruments brought OTP to MOS technology in the 1970s, Kilopass brought OTP to CMOS in 2001, and in 2005 Sidense introduced a low power split channel antifuse device. A Split Channel bit cell combines the thick and thin gate oxide devices into one transistor (1T) with a common polysilicon gate. That little history lesson was more for me than you by the way since I have not worked with non-volatile memory (NVM) since the Virage Logic days.
During my recent worldly travels FinFETs were all the rage but it was repeatedly mentioned that 14nm and more importantly 10nm is “challenging” for both EDA tools and semiconductor IP. This time it was not just “will our design yield?” which is always a concern, but it was also “will our IP work?” Getting the answers to those and other modern semiconductor design questions is of course the whole point behind the TSMC Open Innovation Platform Ecosystem Forumto be held this year on September 17[SUP]th[/SUP] at the Santa Clara Convention Center. Remember, TSMC has completed 15 reference flows with 7,500+ tech files, 200+ PDKS, and more than 8,600 silicon proven IP titles from .35u to 10nm. If you have EDA or IP questions this is the place to be, absolutely.
Back to OTP, one of the first TSMC IOP partner presentations is by Sidense R&D Director, Betina Hold, and is titled:
Ultra Low Power OTP Design for Smart Connected Universe Applications
Betina has spent the majority of her 25+ year career at ARM so she knows low power. Here is the abstract:
Sidense innovative low-voltage Non-Volatile Memory (NVM) designs targeting TSMC Ultra Low Power (ULP) and FinFET process nodes enable a wide range of Smart Connected ICs, spanning several key market segments including IoT, mobile computing, wearable technology, automotive, industrial and medical.
Smart Connected applications need embedded NVM to meet stringent power and reliability requirements. These requirements often include operation from low-voltage battery sources, extended battery life, and operation in safety-critical and/or harsh environmental conditions, and high reliability and extended temperature range are necessary attributes.
This presentation will discuss how the latest OTP IP developments from Sidense address these demands with innovative designs and a 3D 1T-OTP bit cell developed for the most advanced TSMC process nodes.
Along with the low-power properties of Sidense’s patented antifuse-based 1T-OTP bit cell, Betina will also discuss how the right macro design can result in low read voltages along with low power, critical attributes for many Smart Connected applications. She will also cover double-fin FinFET design which has shown significantly lower leakage current, higher programmed cell current, and very high read margin compared to 28nm/20nm bulk CMOS.
I hope to see you there!