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Why You Really Need Chip-Package Co-analysis

Why You Really Need Chip-Package Co-analysis
by Daniel Payne on 08-28-2015 at 12:00 pm

There’s only one software company that I know of that covers four major disciplines: Fluids, Structures, Electronics and Systems. That company is ANSYS and when they acquired Apache Design Automation back in 2011 they filled out their products for electronics design, and more specifically in the area of integrated chip-package co-analysis. I just reviewed a presentation from ANSYS given at DAC back in June titled, Achieving Faster Power Design Closure with Integrated Chip-Package Co-analysis. The historic approach in EDA was to have separate tools for the IC designer, package designer and PCB designer, leading to silos of data that didn’t easily talk to each other, let alone do any co-analysis. Apache saw the opportunity and basically created a new category of EDA tool to support integrated chip-package co-analysis.

Related – Will your next SoC fail because of power noise integrity in IP blocks?

The actual co-analysis is for the Power Delivery Network (PDN) and thermal across the IC and Package domains combined. The premise is that at the IC level you cannot simplify and assume an ideal package for PDN and thermal, because you would be missing the interactions between IC and package, leading to under-design and failed silicon. Having to re-spin silicon is simply too expensive today, so having a co-analysis for PDN and thermal across IC and Package during the design phase helps ensure first silicon success.

At ANSYS the software tool used for power closure is called RedHawk and it provides quite a wide range of checks for power noise and reliability:

With the ANSYS approach you create both a chip model and a package model for PDN and thermal co-analysis. This then allows a designer to do a package-aware chip simulation, plus a chip-aware package optimization:

The benefits of this co-analysis are many:

  • Measuring the package impact on IC
  • Knowing the IC impact on package
  • The IC and package can be co-designed, instead of separately design, in less time
  • System level transient analysis
  • System AC impedance
  • System resonance is known
  • System decap requirements can be validated and optimized

If you ran a transient analysis on your IC and didn’t include package modeling, then the simulated results would look much better than what silicon reported. Here’s a quick comparison of transient analysis for an IC without package models and with package models:

The hot-spots shown on the right where the package models are included while doing transient analysis on the IC clearly show that you must do co-analysis including both IC and package models to get accurate results. When you run IC and Package co-analysis it provides:

  • Support for IR drop, DvD (Dynamic Voltage Drop) and Power-up analysis
  • DC-IR static analysis of the package
  • AC-hotspot analysis of the package

Likewise, by adding package modeling during SoC analysis you get:

  • 3D full-wave accuracy
  • Chip/Package connection is automatically specified
  • Modeling of the power and ground supplies independently
  • Per-bump resolution granularity

Related – How PowerArtist Interfaces with Emulators

Consider what happens if you assume that all your power or ground package bumps are lumped together versus modeled as independent, per-bump. With a lumped approach the bump voltage is only 13.8mV, however with the per-bump model you get a more accurate worst-case of 19.2mV.


Divide and conquer is an approach that no longer works with IC and Package design, so today you should consider using a co-analysis approach to get the most accurate results. ANSYS has been around the longest time in our industry, engineering software tools like RedHawk that support a chip-package co-analysis flow.


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