As chips for any design are fabricated, it turns out that no two are the exactly the same. This is both a blessing and a curse. Current silicon fabrication technology is amazingly good at controlling factors that affect chip to chip uniformity. Nevertheless, each chip has different characteristics. The most extreme case of happens with chips that fail to meet timing. Next in line are chips that perform better or worse than others. I’ll touch on these kinds of differences and the implications a bit later. However, there is another reason to want to discern among unique chips from the same mask set.
If individual chips can be distinguished securely, it creates the potential to enable many important capabilities. If each chip can be given a unique and unalterable and non-duplicable identity, it enables secure boot, cloning protection, keyed feature upgrades and configurability, and secure encryption and decryption. The short version is that we want to transfer publicly viewable but encrypted information to a specific unique IC that is the only device that can decrypt that information. A prevalent way to do this is with public-private key encryption.
However, we have a chicken and egg problem. If all the chips that roll off the production line are identical how can we seed the chips with unique secure keys so they can bootstrap the security process? We need some kind of non-volatile storage that can be easily provisioned in silicon and easily written to right after fabrication. If the key is going to be verifiable and non-clonable, there needs to be hash data to verify it and the on-chip storage must prevent reverse engineering of the data.
Because this level of security is just as important for smaller and low volume IoT designs as it is for large high volume consumer chips, the non-volatile memory must also be cost effective and easy to implement. This rules out many technologies like Flash-NAND, eFuse, etc. They can add the need for additional process layers, complex write support circuitry, external power pads and so on.
Many people are turning to one time programmable (OTP) NVM, like that offered by Sidense. It avoids these pitfalls and offers a high degree of flexibility. To facilitate this Sidense has partnered with Intellitech to provide a complete solution for externally writing security information to on-chip OTP NVM using the IEEE 1149.1-2013 standard. This is done using a JTAG TAP or an SPI interface that is easily added to the chip, and most likely already used for other JTAG functions.
Coming back to the topic of performance variations in chips, we should look at how chips are graded for different applications. It is a common practice to test chips to evaluate their individual speed and thermal performance. The failing chips are discarded – hopefully for good. The rest are often graded and sold for different end applications. Some are sold for higher prices because they run faster. Other better performing parts are used in systems that require higher reliability, such as aircraft, cars or military equipment.
However, there are many instances of lower performing chips illicitly relabeled as higher performance parts. Or even worse, failed parts have been put back into the supply chain. The customary method of indicating the grade of a part after testing is by marking the package. Package markings can be altered, leading to expensive quality and reliability issues in final assembled systems. What is needed is a system for storing part grading within the parts in a tamperproof format.
Once again IEEE 1149.1-2013 offers assistance through its Electronic Chip ID (ECID) specification. ECID allows on chip storage of test results, temperature and speed grade, wafer number, die xy, location and other information. The storage area for ECID can be used for private information as well. By using ECID, it is possible ensure that genuine and correct parts are being used in systems. It also enables a number of key reliability activities. If there are field issues, the wafer lot and die location information can be fed back to the supplier to help resolve quality issues.
ECID is another area that Sidense and Intellitech have focused on. Their complete solution provides for secure writing of the ECID data block. Intellitech also offers user level software and interface boards that allow for easy reading of the ECID information so it can be used to verify parts before they are soldered to a board. Additionally, in the case of failures, it is possible to read out the information needed for resolving reliability issues.
IEEE 1149.1-2013 is playing a major role in adding value and preventing fraud in the supply chain. With a solution like the one proposed by Sidense and Intellitech, it becomes feasible to maximize the benefits of ECID and to ensure that chips for niche markets can have security features matching larger mainstream SOC’s. After all, the most likely target for a security attack would be edge node chips that might not be designed with robust security.
Sidense OTP-NVM has a multitude of features to prevent reverse engineering, side-channel attacks. They also can come with completely self-contained write logic that can work with system supply voltages. This, and the requirement for no additional layers makes it an excellent choice for implementing ECID, and key and feature configuration storage. More detailed information about how the Sidense and Intellitech joint solution works can be found on the Sidense Website.