Top 10 Updates from the TSMC Technology Symposium, Part I

Top 10 Updates from the TSMC Technology Symposium, Part I
by Tom Dillinger on 03-22-2017 at 7:00 am

Image RemovedLast week, TSMC held their 23rd annual technical symposium in Santa Clara. In the Fall, TSMC conducts the OIP updates from EDA/IP partners and customers. The theme of the Spring symposium is solely on TSMC’s technology development status and the future roadmap. Indirectly, the presentations also provide… Read More


When Talking About IoT, Don’t Forget Memory

When Talking About IoT, Don’t Forget Memory
by Tom Simon on 11-13-2015 at 7:00 am

Memory is a big enough topic that it has its own conference, Memcon, which recently took place in October. While I was there covering the event for SemiWiki.com I went to the TSMC talk on memory technologies for the IoT market. Tom Quan, Director of the Open Innovation Platform (OIP) at TSMC was giving the talk. IoT definitely has special… Read More


Cadence Outlines Automotive Solutions at TSMC OIP Event

Cadence Outlines Automotive Solutions at TSMC OIP Event
by Tom Simon on 10-08-2015 at 12:00 pm

I used to joke that my first car could survive a nuclear war. It was a 1971 Volvo sedan (142) that was EMP proof because it had absolutely no semiconductors in the ignition system, just points, condensers and a coil. If you go back to the Model T in 1915 you will see that the “on-board electronics” were not that different. However, today… Read More


New Sensing Scheme for OTP Memories

New Sensing Scheme for OTP Memories
by Paul McLellan on 09-22-2015 at 7:00 am

Last week at TSMC’s OIP symposium, Jen-Tai Hsu, Kilopass’s VP R&D, presented A New Solution to Sensing Scheme Issues Revealed.

See also Jen-Tai Hsu Joins Kilopass and Looks to the Future of Memories

He started with giving some statistics about Kilopass:

  • 50+ employees
  • 10X growth 2008 to 1015
  • over 80 patents (including
Read More

TSMC OIP: What to Do With 20,000 Wafers Per Day

TSMC OIP: What to Do With 20,000 Wafers Per Day
by Paul McLellan on 09-17-2015 at 4:42 pm

Image RemovedToday it is TSMC’s OIP Ecosystem Innovation forum. This is an annual event but is also a semi-annual update on TSMC’s processes, investment, volume ramps and more. TSMC have changed the rules for the conference this year: they have published all the presentations by their partners/customers. Tom Quan… Read More


Ultra-Low Power Non-Volatile Memory Solutions for the Smart Connected Universe

Ultra-Low Power Non-Volatile Memory Solutions for the Smart Connected Universe
by Tom Simon on 06-01-2015 at 6:00 pm

DAC is a great place to gather information about products and technologies. However it can be difficult to chase down the information you need because you may need to cover a lot of ground to hear or talk to the people with the right knowledge. Fortunately there are a few places you can go to learn about a number of products at one place.… Read More


TSMC 10nm Readiness and 3DIC

TSMC 10nm Readiness and 3DIC
by Paul McLellan on 05-03-2015 at 1:00 am

Image RemovedAt the TSMC Technology Symposium last month Suk Lee presented a lot of information on design enablement. Suk is an interesting guy with a unique background in ASIC, Semiconductor, EDA, and now Foundry. In baseball terms that would be like playing infield, outfield, home plate, and umpire!

Around the turn of the millennium… Read More


TSMC’s OIP: Everything You Need for 16FF+ SoCs

TSMC’s OIP: Everything You Need for 16FF+ SoCs
by Paul McLellan on 02-13-2015 at 7:00 am

Image RemovedDoing a modern SoC design is all about assembling IP and adding a small amount of unique IC design for differentiation (plus, usually, lots of software). If you re designing in a mature process then there is not a lot of difficulty finding IP for almost anything. But if you are designing in a process that has not yet reached… Read More


TSMC Gets Ready for IoT

TSMC Gets Ready for IoT
by Paul McLellan on 12-10-2014 at 11:36 am

With all the talk about 14/16nm and 10nm it is important to realize that older processes are still important. Eventually 16nm may end up being cheaper than 28nm but for the time being 28nm seems to be a sort of sweet spot, not just cheaper than every process that came before it (which was true for every new node) but also cheaper than every… Read More


Cliff Hou at TSMC OIP

Cliff Hou at TSMC OIP
by Paul McLellan on 10-26-2014 at 7:00 am

Image RemovedI attended Cliff Hou’s keynote at TSMC OIP Forum earlier this month. OIP is a huge undertaking. It currently has over 100 ecosystem partners, 10 technology generations, 7600+ IPs, 60+ EDA tools, 7000+ tech files and 150+ PDKs.

Most of Cliff’s presentation gave details on where TSMC are with the various… Read More