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TSMC’s OIP: Everything You Need for 16FF+ SoCs

TSMC’s OIP: Everything You Need for 16FF+ SoCs
by Paul McLellan on 02-13-2015 at 7:00 am

 Doing a modern SoC design is all about assembling IP and adding a small amount of unique IC design for differentiation (plus, usually, lots of software). If you re designing in a mature process then there is not a lot of difficulty finding IP for almost anything. But if you are designing in a process that has not yet reached high-volume manufacturing (HVM) then there is a new set of challenges. If you are really on the bleeding edge and the volumes are going to justify the cost, then the company has to design its own IP since commercial IP just is not available (think companies like Qualcomm or Apple). For everyone else, they need to wait for a broad portfolio of IP to be available. But they don’t want to wait forever. TSMC has its OIP program to ensure that IP is available as soon as possible, that it is tested in silicon and generally is getting ahead of the curve. After all, TSMC makes money when designs go into production and the critical path for getting a design into production goes right through the middle of having EDA tool flows and IP available. TSMC’s IP ecosystem surpassed the mark of 8,000 registered IPs in 2014, from more than 40 IP partners. TSMC IP Alliance partners, together with TSMC internal IP teams, form the largest and fully qualified IP platform available to IC designers in the world. It is a live ecosystem, constantly evolving to adapt to customer needs. With the new creation of ULP processes targeted to IoT applications, a more comprehensive solution is now necessary. TSMC 3rd party IP vendors will add their expertise, creating updated and new low-power IP for TSMC processes.Last year’s Open Innovation Platform 2014 (OIP) Ecosystem Forum was held in September. Over 1000 customers and partners participated. The main focus was on TSMC’s latest processes, in particular 16FF+. TSMC and its partners made the following announcements:

  • OIP has provided over 12 years of ecosytem enablement
  • a new 28nm 28HPC high performance process offering available
  • 20nm in mass production
  • 16FF+ ready for product design
  • Reference flows for 16FF+ delivered
  • ARM big.LITTLE vaiidated in 16FF+
  • 10FF EDA tools ready for early customer design starts

At the forum, the TSMC OIP Partner of the Year Awards were announced. First for IP:

  • Foundation IP: ARM
  • Interface IP: Synopsys
  • Analog/Mixed-Signal IP: Analog Bits
  • Embedded Memory IP: eMemory Technology
  • Emerging IP Company: Silicon Creations
  • Specialty IP: Dophin Integration
  • Soft IP: Cadence

Then the EDA awards for the joint development of the 16FF+ design infrastructure (alphabetical):

  • Apache business unit of ANSYS
  • AtopTech
  • Cadence
  • Mentor
  • Synopsys

 The key to the diagram above is purple is Synopsys, red is Cadence, green is Mentor (I think of blue being Mentor based on their website), yellow is Apache, blue is Atoptech and pink is Invarian. These tools go to create a digital SoC (synthesis, place & route) reference flow that captializes on 16FF+ PPA through optimized tool and standard cell implementation, with a constraint variation model for accurate timing signoff, a self-heating model to address thermal concerns, rush current analysis for powering blocks down and up, and more. They also create a customer reference flow for custom digital and analog/mixed-signal with a complete “number of fins” methodology to replace length/width of planar processes. The flow takes into account layout dependent effects, voltage dependent rule checks and a full transistor-level electromigration (EM) and IR drop analysis flow for power analysis.The release of new ultra-low-power (ULP) processes at mature nodes to support the upcoming IoT opportunities, does not lower the focus of TSMC on wide set of Foundation, Interface and Soft-IP from both TSMC and its IP Alliance partners for the leading edge.


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