Advanced Semiconductor Process Cost Trends

Advanced Semiconductor Process Cost Trends
by Scotten Jones on 12-13-2016 at 4:00 pm

Image RemovedThe cost trend for leading edge semiconductor technologies is a subject of some controversy in the industry. Cost is a complex issue with many interacting factors and much of the information out in the industry is in my opinion misleading or incorrect. In this article, I will discuss each of the factors as well as present… Read More


SEMICON West – Globalfoundries Update

SEMICON West – Globalfoundries Update
by Scotten Jones on 08-14-2016 at 12:00 pm

Image RemovedOn Wednesday of SEMICON West I got to sit down with Gary Patton, CTO of GlobalFoundries and get an update on what has been going on with them.

Gary started the interview by pointing out that it has now been a year since the GlobalFoundries purchase of many of IBM’s semiconductor assets and they have hit every commitment… Read More


SEMI SMC: Atoms Still Don’t Scale

SEMI SMC: Atoms Still Don’t Scale
by Paul McLellan on 09-24-2015 at 7:00 am

Image RemovedLast Tuesday was the SEMI’s annual Strategic Materials Conference (SMC). The opening keynotes were given by Gary Patton, the CTO of GlobalFoundries, and Mark Thirsk, Managing Partner of Linx Consulting. This year it was held in the Computer History Museum (which always makes the commute interesting since… Read More


TSMC OIP: What to Do With 20,000 Wafers Per Day

TSMC OIP: What to Do With 20,000 Wafers Per Day
by Paul McLellan on 09-17-2015 at 4:42 pm

Image RemovedToday it is TSMC’s OIP Ecosystem Innovation forum. This is an annual event but is also a semi-annual update on TSMC’s processes, investment, volume ramps and more. TSMC have changed the rules for the conference this year: they have published all the presentations by their partners/customers. Tom Quan… Read More


Moore’s Law is dead, long live Moore’s Law – part 4

Moore’s Law is dead, long live Moore’s Law – part 4
by Scotten Jones on 04-21-2015 at 11:00 pm

Image RemovedIn the third installment of this series we discussed the status of DRAM scaling and Moore’s law. In this installment we will tackle logic. The focus will be on foundry logic.

Logic technology challenges
In the second installment of this series we discussed constant electric field scaling. As we mentioned in that installment… Read More


Variation Alphabet Soup

Variation Alphabet Soup
by Paul McLellan on 04-04-2015 at 1:00 pm

Image RemovedOn-chip variation (OCV) is a major issue in timing signoff, especially at low voltages or in 20/16/14nm processes. For example, the graph below shows a 20nm inverter. At 0.6V the inverter has a delay of 2 (nominalized) units. But due to on-chip variation this might be as low as 1.5 units or as high as 3 units, which is a … Read More


FD-SOI Foundry

FD-SOI Foundry
by Paul McLellan on 03-16-2015 at 7:00 am

Image RemovedAt the end of last month during ISSCC there was a forum organized by the SOI Consortium. It took place in San Francisco at the Palace Hotel (which, if you have never been there, is famous for converting its old entryway for carriages into an amazing dining room, and for a bar with a huge painting by Maxfield Parrish of the… Read More


TSMC’s OIP: Everything You Need for 16FF+ SoCs

TSMC’s OIP: Everything You Need for 16FF+ SoCs
by Paul McLellan on 02-13-2015 at 7:00 am

Image RemovedDoing a modern SoC design is all about assembling IP and adding a small amount of unique IC design for differentiation (plus, usually, lots of software). If you re designing in a mature process then there is not a lot of difficulty finding IP for almost anything. But if you are designing in a process that has not yet reached… Read More


Altera Back to TSMC at 10nm? Xilinx Staying There

Altera Back to TSMC at 10nm? Xilinx Staying There
by Paul McLellan on 01-28-2015 at 7:00 am

Image RemovedXilinx announced their quarterly results last week. They slightly missed their number due mainly to a decline in wireless sales. Of course Xilinx parts don’t go in the smartphones since the cost and power are too high, but they are very heavily used in basestation, backhaul etc especially in China. Xilinx’s… Read More


Will the Apple A9 Fall Flat?

Will the Apple A9 Fall Flat?
by Robert Maire on 01-23-2015 at 12:00 pm

Image RemovedSeveral months ago we had suggested that we were concerned that Apple’s A9 processor would wind up being 20nm planar (maybe 14nm planar) rather than the expected 14nm FinFET. As we are now under 9 months from a likely launch time for Apple’s next gen IPhone the timing for getting a 14nm FinFET processor Read More