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TSMC OIP: What to Do With 20,000 Wafers Per Day

TSMC OIP: What to Do With 20,000 Wafers Per Day
by Paul McLellan on 09-17-2015 at 4:42 pm

 Today it is TSMC’s OIP Ecosystem Innovation forum. This is an annual event but is also a semi-annual update on TSMC’s processes, investment, volume ramps and more. TSMC have changed the rules for the conference this year: they have published all the presentations by their partners/customers. Tom Quan of TSMC told me that they will also provide a subset of the presentations TSMC gave to open the day.

The semiconductor business is driven by several large markets, the biggest of which is mobile. Fun statistics of the day are that mobile grew 26% from 2014-15 to shipments of 1.9B units. Since there are 4.3B worldwide mobile users, this means that the annual replacement rate is close to 50%. Global mobile traffic is forecast to go up 10X in 5 years from 30EB/yr in 2014 to 292EB/yr in 2019 (EB is exabyte).

For the future, the three big markets other than mobile are Internet of Things (IoT), Automotive, and High-performance Computing (HPC).

Let’s start with IoT: the market has a forecast CAGR from 2013 to 2018 of 21%. But the market is ripe in that 99.4% of devices are notconnected, so by 2022 the average house is forecast to have 500 smart devices. Of course every time you blink the IoT forecast goes up by a billion units but for sure it is real.

The big opportunity in automotive in the medium term is driverless cars or, before that, advanced driver assist systems (ADAS). Google’s driverless cars have done over 2M miles (with 16 minor accidents, all the fault of the other vehicle). Delphi/Audi drove a vehicle across the US from SF to NY (that I wrote about during DAC). Tesla will have autopilot in all their cars. One interesting potential change that autonomous vehicles might bring is to ownership. If you could have a car on-demand whenever you wanted one, would you own your own vehicle at all. Your car plan in a decade might be like your cellphone plan today, with various options depending on usage.

HPC is required to provide the back-end for all those mobile devices, typically in large datacenter aka cloud computing. The need for low latency and location awareness means that the mobile device needs to be providing local intelligence, but then low latency connect to the datacenter will be required too. This means that there will be upgrade cycles to all the base stations, of which there are (literally) millions.

TSMC provides a wide range of processes for different types of silicon. The process nodes mentioned here are where TSMC is working on bringing the process up; volume production is one (or sometimes two) nodes behind.

[TABLE] class=”cms_table_outer_border” style=”width: 240px”
| class=”cms_table_outer_border_td” | Application
| class=”cms_table_outer_border_td” | Technology
|- class=”cms_table_outer_border_tr”
| class=”cms_table_outer_border_td” | MEMS
| class=”cms_table_outer_border_td” | 0.13um
|- class=”cms_table_outer_border_tr”
| class=”cms_table_outer_border_td” | Image Sensor
| class=”cms_table_outer_border_td” | 40nm
|- class=”cms_table_outer_border_tr”
| class=”cms_table_outer_border_td” | Embedded flash
| class=”cms_table_outer_border_td” | 28nm
|- class=”cms_table_outer_border_tr”
| class=”cms_table_outer_border_td” | RF
| class=”cms_table_outer_border_td” | 16nm
|- class=”cms_table_outer_border_tr”
| class=”cms_table_outer_border_td” | Logic
| class=”cms_table_outer_border_td” | 7nm
|- class=”cms_table_outer_border_tr”
| class=”cms_table_outer_border_td” | Analog
| class=”cms_table_outer_border_td” | 16nm
|- class=”cms_table_outer_border_tr”
| class=”cms_table_outer_border_td” | High voltage
| class=”cms_table_outer_border_td” | 40nm
|- class=”cms_table_outer_border_tr”
| class=”cms_table_outer_border_td” | Embedded DRAM
| class=”cms_table_outer_border_td” | 40nm
|- class=”cms_table_outer_border_tr”
| class=”cms_table_outer_border_td” | BCD/power
| class=”cms_table_outer_border_td” | 0.13um

R&D overall is up 19% year-on-year from 2014 to 2015. It was $1.9B in 2014 and will be $2.2B in 2015. OIP has grown and now has over 200 PDKs, 7500 technology files and 8500 IP blocks. The wafers enabled by this IP grew at a CAGR of 22% from 2005-14. Capex is up 10-16% from 2014 to about $10.5B to $11B, compared to $9.5B last year. Total capacity is 1.6M 8″ equivalent wafers per month, over 20,000 per day, up 12% year-on-year.

UPDATE: I totally messed up the title of this blog and the computation. It is over 50,000 wafers per day or over 200 per hour.

New processes are ramping faster than ever. N40 ramped in 35 months. N28 ramped in 22 months. N20 ramped in 3 months. N16 is ramping even faster. At this rate volume production will be faster than qual!

The second presentation was by Jack Sun, TSMC’s CTO. I tried to take notes on the processes but there was too much information. I’ll revisit this once I get some slides to work from. But in the meantime, here are a few highlights.

  • N10 will be risk production in Q4 of 2015. Development is on-track.
  • N7 will be risk production Q1 of 2017. SRAM test-chip is functional.
  • 16FFC will be risk production in Q2 2016
  • 16FF+ is in volume production, with a couple of dozen takeouts and 50 more expected before end of year

The key new process coming soon is 16FFC, which is the third generation of 16nm process. Speedup is 65% vs 28nm and 40% vs 20nm. Or a power saving for 70% vs 28nm or 60% vs 20nm. It can go down to 0.55V. TSMC have repeatedly stated that 16FFC will be a long-lived node, which I take to mean that 16FFC will be cheaper per transistor than N28. The design rules are the same so migrating designs and IP should be fairly straightforward. There is a new library coming that will allow operation down to 0.4V, with a focus on minimizing the non-gaussian variation.

N10 has a scale factor of 50% versus 16FF+, with a performance improvement of 20% or a power saving of 40%. There are 3 different Vt and gate-length bias covering a wide range of leakage/speed envelopes. N10 SRAM is yielding well, SERDES runs at 56Gbps with 22% better power efficiency than 16FF+.

N7 has a further speed improvement of 10-50% versus N10, or a power saving of 25-30%. It will be 1.6X the density. Risk production will be Q1 of 2017. Initially libraries for mobile, but new second generation libraries with taller cells for HPC. Special SRAM for HPC too, with 25% better performance. There is an ARM Cortex-A57 test chip showing 40-45% are reduction.

But the roadmap doesn’t end there. TSMC is doing research on Ge FinFET, III-V NFET, gate-all-around nanowires, 2D crystal, directed self-assembly, multi-e-beam direct write, inverse computational lithography. And, of course, EUV. TSMC have achieved 90W source power in-house. ASML have demonstrated 130W. They are working jointly to get all the settings worked out for 125 wafer/hour production.

Other segments. CMOS Image Sensor (CIS):

  • FSI front image sensor
  • BSI back image sensor (the die is thinned and the light comes through the back)
  • BSI/ISP back image sensor flipped onto an image signal processor
  • NIR near-infra-red


  • accelerometer
  • pressure sensor
  • motion sensor
  • microphone
  • new gas sensors
  • new biometric sensors

Emerging new memories:

  • eRRAM
  • eMRAM

This is all from my handwritten notes. If you spot errors then correct me in the comments.

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