The cost trend for leading edge semiconductor technologies is a subject of some controversy in the industry. Cost is a complex issue with many interacting factors and much of the information out in the industry is in my opinion misleading or incorrect. In this article, I will discuss each of the factors as well as present a view of the status and a future forecast.
The first element in evaluating cost, is wafer cost. My company – IC Knowledge LLC is the world leader in cost modeling of Semiconductors and MEMS. Our IC Cost and Price model has been out in the industry since 2000 and is the industry standard for semiconductor cost and price analysis. Our customer list is a who’s who of IDMs, fabless companies, foundries, electronics companies, analysts and others. We have a variety of methods that allows us to check our model results against actual industry results and since Q1 of 2000 our modeling is consistently within a few percentage points of actual results. We also offer a Strategic Cost Model that forward projects the next several generations of semiconductor technology.
There is no question that wafer costs are rising. Metal layers have increased from a typical of 6 layers at 130nm node to a forecast of 14 metal layers at the 5nm node. Starting at the 90nm node strain was introduced to continue to scale performance. Between 45nm and 28nm we have seen logic processes transition to high-k metal gates. We have seen an increase in typical number of threshold voltages from 2 to 5. From 40nm until the transition to FinFETs at the 16nm/14nm node, short channel effects increased the complexity of threshold voltage control driving up the number of implants required. As previously mentioned at the 16nm/14nm node FinFETs have been introduced and we may see another new technology such as stacked horizontal nanowires at 5nm (3.5nm at foundries). Starting at 20nm increasingly complex multi-patterning schemes have been required and somewhere between the 7nm and 5nm node we will likely see EUV introduced.
All of these factors drive up complexity and cost. For the cost projections we will present, we have chosen to base our discussion on our estimates for TSMC. Slide 1 presents TSMC processes from 130nm to 5nm with selected structural parameters.
Slide 2 converts the process parameters from slide 1 into the required mask counts by node broken out between mask layers and cut/block masks required for multi-patterning.
For these structural parameters and mask counts we can calculate wafer costs. In slide 3 we present the wafer cost by node on the left side, cell density in the center and the resulting cost per cell on the right side.
For wafer cost there are really three distinct cost trend regions. From 130nm to 65nm the cost trend is due to “normal” complexity increases. From 40nm down to around 20nm there is an increased rate of cost change due to the difficulties of short channel control, growing number of threshold voltages and other performance scaling issues. Then after 20nm we see the rate of increase rise again due to multi-patterning.
Increasing process complexity is being implemented to produce improved performance and density. In order to determine the effect of rising wafer costs we need to determine the resulting cell density. The size and density of the cells utilized as circuit building blocks is determined by the contacted poly pitch (CPP) in one direction and the minimum metal pitch (MMP) multiplied by the number of tracks in the other directions. The smaller the number of tracks the smaller the cell, but the smaller the number of tracks the more difficult routing becomes.
Up through the 16nm node we have actual density values for TSMC and during quarterly conference calls TSMC has disclosed their expected density improvements for their 10nm, 7nm and 5nm processes.
The middle graph in slide 3 presents TSMC’s process density by node.
The density presented is the “gross” density and does not factor in yield. There are some claims in the industry that yields are going down with each new node. We do not agree with this. Certainly, there have been some well published yield issues, for example Intel at 14nm but we believe that mature yields are still achieving values consistent with previous generations.
Cost Per Cell
By combing the normalized wafer cost from the left side of slide 3 with the cell density presented in the center graph on slide 3, we can produce a cost per cell and that is presented on the right side of slide 3.
The results in slides 3 for wafer cost, density and cell cost are consistent with the results Intel has published during their investor calls indicting that we believe TSMC is able to also achieve continuing cost reductions.
Most modern designs have a power budget. As transistor densities have grown the power for performance for the denser processes hasn’t kept pace and in many designs not all of the transistors can be turned on at the same time. The transistors that are left off to manage the power budget are referred to as dark silicon. However, dark silicon is not wasted silicon, dark silicon is typically used to create accelerators that are only turned on as needed. Ideally the power performance of each new node would be such that all the transistors could be left on optimizing performance but the dark silicon isn’t always dark and isn’t wasted area.
With each new process node design costs have been sky rocketing. This has created a situation where less and less designs each year have enough volume to be able to support the cost of the design. The cost of a design must be amortized over the number of parts produced and in all but the highest volumes leading edge designs are no longer economically viable.
In spite of the challenges of developing leading edge processes the manufacturing cost for a cell continues to fall. There is however a significant issue with high design costs creating a barrier to entry that only the highest volume products can scale.