Mentor at TSMC OIP, 16nm, and 10nm

Mentor at TSMC OIP, 16nm, and 10nm
by Beth Martin on 09-26-2014 at 4:46 pm

On Tuesday, September 30, TSMC hosts another Open Innovation Platform Ecosystem forum at the San Jose Convention Center. Have you registered? This year includes 30 technical sessions from TSMC’s ecosystem partners, divided into three separate tracks. I’ll be hanging out in the EDA track, listening to various takes on 16nm FinFET… Read More


TSMC OIP: Registration Open

TSMC OIP: Registration Open
by Paul McLellan on 09-06-2014 at 9:00 am

Image RemovedIt’s that time of year again! The 4th TSMC Open Innovation Platform Ecosystem Forum is coming up on September 30th. As usual it is in the San Jose conference center. The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and their customers to share real case solutions to today’s… Read More


TSMC: Keynote, OIP, 20nm, 16nm, panels, and more #51DAC

TSMC: Keynote, OIP, 20nm, 16nm, panels, and more #51DAC
by Paul McLellan on 05-28-2014 at 8:11 pm

Image RemovedWhat is TSMC doing at DAC?

The biggest event is presumably Cliff Hou’s DAC keynote on Monday at 3.25pm Industry Opportunities in the Sub-10nm Era. And he also wrote the foreword to Fabless, the book that Dan Nenni and I have written and where you can get a signed copy on Tuesday evening at the reception.

There is … Read More


TSMC OIP presentations available!

TSMC OIP presentations available!
by Beth Martin on 01-27-2014 at 6:27 pm

Are you a TSMC customer or partner? If so, you’ll want to take a look at these presentations from the 2013 TSMC Image RemovedOpen Innovation Platform conference:

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ESD at TSMC: IP Providers Will Need to Use Mentor to Check

ESD at TSMC: IP Providers Will Need to Use Mentor to Check
by Paul McLellan on 01-22-2014 at 1:24 pm

Image RemovedI met with Tom Quan of TSMC and Michael Beuler-Garcia of Mentor last week. Weirdly, Mentor’s newish buildings are the old Avant! buildings where I worked for a few weeks after selling Compass Design Automation to them. Odd sort of déja vu. Historically, TSMC has operated with EDA companies in a fairly structured… Read More


A Brief History of TSMC’s OIP part 2

A Brief History of TSMC’s OIP part 2
by Paul McLellan on 09-18-2013 at 11:00 pm

The existence of TSMC’s Open Innovation Platform (OIP) program further sped up disaggregation of the semiconductor supply chain. Partly, this was enabled by the existence of a healthy EDA industry and an increasingly healthy IP industry. As chip designs had grown more complex and entered the system-on-chip (SoC) era, the amount… Read More


TSMC’s 16FinFET and 3D IC Reference Flows

TSMC’s 16FinFET and 3D IC Reference Flows
by Paul McLellan on 09-17-2013 at 2:01 am

Today TSMC announced three reference flows that they have been working on along with various EDA vendors (and ARM and perhaps other IP suppliers). The three new flows are:

  • 16FinFET Digital Reference Flow. Obviously this has full support for non-planar FinFET transistors including extraction, quantized pitch placement, low-vdd
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TSMC OIP: Mentor’s 5 Presentations

TSMC OIP: Mentor’s 5 Presentations
by Paul McLellan on 09-09-2013 at 6:30 pm

At TSMC’s OIP on October 1st, Mentor Graphics have 5 different presentations. Collect the whole set!

Image Removed11am, EDA track. Design Reliability with Calibre Smartfill and PERC. Muni Mohan of Broadcom and Jeff Wilson of Mentor. New methodologies were invented for 28nm for smart fill meeting DFM requirements (and… Read More


A Brief History of TSMC OIP

A Brief History of TSMC OIP
by Paul McLellan on 09-01-2013 at 9:00 pm

Image RemovedThe history of TSMC and its Open Innovation Platform (OIP) is, like almost everything in semiconductors, driven by the economics of semiconductor manufacturing. Of course ICs started 50 years ago at Fairchild (very close to where Google is headquartered today, these things go in circles). The planarization approach,… Read More


Tag it! Your customer will love using IP compliant with TSMC9000 IP Tag specification

Tag it! Your customer will love using IP compliant with TSMC9000 IP Tag specification
by Eric Esteve on 05-16-2013 at 1:26 am

We have seen last week in a first post how crucial was the IP qualification process (TSMC 9000) to increase the probability of successfully Tape Out a chip. Being able to discriminate between dangerous and safe IP is the first step of TSMC 9000 Quality process, IP tagging is the complementary step, almost as essential as the first … Read More