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Cliff Hou at TSMC OIP

Cliff Hou at TSMC OIP
by Paul McLellan on 10-26-2014 at 7:00 am

 I attended Cliff Hou’s keynote at TSMC OIP Forum earlier this month. OIP is a huge undertaking. It currently has over 100 ecosystem partners, 10 technology generations, 7600+ IPs, 60+ EDA tools, 7000+ tech files and 150+ PDKs.

Most of Cliff’s presentation gave details on where TSMC are with the various processes. Of course 20nm and above is all in full production, and we know it is shipping in high volume to both Apple and Qualcomm, among others, since they have said so. In fact there are 12 products that are already function proven on first silicon.


16FF completed full qualification in Q4 2013 and entered production. Over 55 products are planned for tapeout in 2014/5 in mobile, networking, CPU, GPU, FPGA and more. They achieved first silicon success on a network processor for HiSilicon Technologies. It is actually a combination of several chips using TSMC’s CoWoS (chip-on-wafer-on-silicon) 3D technology. The logic chips are built on 16FF process containing 32 Cortex-A57 cores, and the second chip is a 28nm I/O chip.

16FF+ (the “+” is important, it is a different process) is currently in qualification, which is on track. They released V1.0 in August 2014 so designs can start. 16FF+ yield is ahead of plan.


The 16FF+ IP ecosystem is already showing silicon results with various interface and memory IP already completed silicon qualification.

Cliff talked about 10nm. He said that it has industry leading density for the smallest die size. Compared to 16FF+ it has a speed improvement of 25%, a power reduction of 45%, density improvement of 2.2X for logic and 0.45X for SRAM. The key upcoming milestones are:

  • V0.1 available for design starts Q4 2014
  • V0.5 available, Q2 2015
  • Risk production November 2015


Going off the bleeding edge, Cliff talked about TSMC’s ultra-low-power technology, especially targeted at internet of things (IoT) applications:

  • 0.18eLL and 90uLL in production
  • 55ULP, 40ULP and 28ULP will have risk production in 2015
  • RF and embedded flash features for IoT SoC integration
  • The ULP processes have lower Vdd to reduce active and standby power. Tailored eHVT device enables over 70% reduction in standby power. Think battery life.

Cliff’s last slide summarized TSMC’s process introduction roadmap:

  • 16FF+ is mature and ecosystem ready with multiple solutions. First product is silicon-proven with 50+ tape-outs are scheduled for 2014 and 2015
  • 10nm offers 2.2X gate density, 25% better speed or 45% power reduction with risk production in Q4 2015. Ecosystem solutions have been developed, certified and in use on test chips
  • Ultra Low Power technology platform, covering from 0.18ɥm to 28ULP, can support various IoT applications. Existing ecosystem can be leveraged for fast time-to-market