Are you a TSMC customer or partner? If so, you’ll want to take a look at these presentations from the 2013 TSMC Open Innovation Platform conference:
- Design Reliability with Calibre YE-SmartFill and Calibre PERC (Broadcom & Mentor Graphics)
New methodologies were developed for 28nm designs using Calibre SmartFill and Calibre PERC. Calibre SmartFill was deployed to meet the new strict DFM requirements while reducing run time, file size and iterations. Design consistency checks written with rules in Calibre PERC were implemented to catch design mistakes early in the design flow process, and validate high reliability design metrics.
- Synopsys Laker Custom Layout and Calibre Interfaces: Putting Calibre Confidence in Your Custom Design Flow (Mentor Graphics)
Through close cooperation between Mentor and Synopsys, Synopsys Laker users can check with Calibre “on the fly” during design to speed creation of design-rule correct layout, including electrically-aware voltage-dependent DRC checks.
- Verify TSMC 20nm Reliability Using Calibre PERC(Mentor Graphics)
Calibre PERC was used in close collaboration with TSMC IO/ESD team to develop an automatic verification kit to verify CDM ESD issues for the N20 node.
- EDA-Based DFT for 3D-IC Applications (Mentor Graphics)
Testing of TSMC’s 2.5D/3D ICs implies changes to traditional Built-In Self-Test (BIST) insertion flows provided by commercial EDA tools. Tessent tools provide a number of capabilities that address these requirements while reducing expensive design iterations or ECOs, which ultimately translates to a lower cost per device.
- Advanced Chip Assembly & Design Closure Flow Using Olympus-SoC (Mentor Graphics & NVIDIA)
Mentor and NVIDIA discuss the chip assembly and design closure solution for TSMC processes, including concurrent MCMM optimization, synchronous handling of replicated partitions, and layer promotion of critical nets for addressing variation in resistance across layers.