WP_Term Object
(
    [term_id] => 71
    [name] => Xilinx
    [slug] => xilinx
    [term_group] => 0
    [term_taxonomy_id] => 71
    [taxonomy] => category
    [description] => 
    [parent] => 106
    [count] => 110
    [filter] => raw
    [cat_ID] => 71
    [category_count] => 110
    [category_description] => 
    [cat_name] => Xilinx
    [category_nicename] => xilinx
    [category_parent] => 106
)

Xilinx’s Mixed Signal FPGA

Xilinx’s Mixed Signal FPGA
by Luke Miller on 01-28-2014 at 10:00 am

Something in all the Xilinx chatter of UltraScale 20nm, 16nm, having massive amounts of Gigabit transceivers, DSP blocks, RAM, HLS, Rapid Design Closure gets lost… and that is Xilinx’s ability for Mixed Signals. I do not mean when you are talking with the wife (Remember Listen!), but a wonderful block that lives within the 7 series of Xilinx FPGAs. It is called ‘XADC’, what it does is marvelous and once again using Xilinx allows more of the board design, integration, cost and time to market (The FPGA Blob strikes again…) to be absorbed by the Xilinx FPGA. Let me explain…

In the ‘Internet of things’ and everything else around us, is a desire for sensor fusion and we live in an analogue world. Everything needs to be monitored. Power, current, voltage, temperature, humidity, velocity, acceleration, jerk, jolt, jounce, kid’s attitudes, sampling audio streams, heart rates, blood pressure, glucose levels, distance, light intensity, flow meters and this list can keep going. All the above sensors as most, unless we are doing some RADAR/EW design, LTE or Medical design, we do not need 3 GHz sample rates and beyond. So just for a few moments think my friend, about all that you can do! In one Xilinx part nonetheless.

Below is the block diagram of the XADC in the Xilinx 7 series FPGAs. It is a very powerful core and important as we can now think of the FPGA not as just a piece of digital processing but truly mixed signal processing. That is not a trivial task.

Above you will see are dual 12-bit, 1 Mega sample per second (MSPS) ADCs. The dual ADCs support a range of operating modes, such as externally triggered and simultaneous sampling on both ADCs and various analog input signal types, for example, single ended. The ADCs can access up to 17 external analog input channels. All of the channels are available to your FPGA design. Of course the channels are time interleaved. They can be triggered or continually round robin sampled. If all this does not excite you, please wire the ADCs to measure your heart rhythm as you may be dead, make sure to filter out any potential 60 Hz noise or higher frequencies from the fluorescent lights. You can use Vivado HLS for the adaptive filter algorithm using QR decomposition. Sorry, I digressed. As for me and my fellow nerds, we are excited!

So you want to try working with the XADC, I know you do! Once again here is where Xilinx shines. There are vast amount of resources, reference designs to allow you in a matter of minutes to get started. I always like video before reading so here is a greatXilinx video to watch. All the details for the XADC are found here in UG480, Zynq included. Now for the bread and butter, the reference design… Here you go, click here. You will need to sign up for a Xilinx account. In this design Xilinx shows the user how to perform analogue simulations which is really, really cool and hopefully our minds will start thinking that Xilinx is just more than Digital!

More articles by Luke Miller…

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