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New Sensing Scheme for OTP Memories

New Sensing Scheme for OTP Memories
by Paul McLellan on 09-22-2015 at 7:00 am

Last week at TSMC’s OIP symposium, Jen-Tai Hsu, Kilopass’s VP R&D, presented A New Solution to Sensing Scheme Issues Revealed.

See also Jen-Tai Hsu Joins Kilopass and Looks to the Future of Memories

He started with giving some statistics about Kilopass:

  • 50+ employees
  • 10X growth 2008 to 1015
  • over 80 patents (including more filed for this new sensing scheme)
  • 179 customers, 400 sockets, 10B units shipped

Kilopass’s technology works in a standard process using antifuse, causing a breakdown of the gate-oxide. Since the mechanical damage is so small it is not detectable even by invasive techniques, unlike eFuse technologies where the breaks in the fuse material are clearly visible by inspection. Over the generations of process nodes they have reduced the power by a factor of 10 and reduced the read access time to 20ns. Since the technology scales with the process, the memory can scale as high as 4Mb. It also is low power and instant-on.

Kilopass has focused on 3 major markets:

  • security keys and encryption. This only requires Kb of memory. The end markets are set-top box, gaming, SSD, military
  • configuration and trimming of analog. This also requires Kb of memory. End markets are power management, high precision analog and MEMS sensors
  • microcode and boot code. This requires megabits to tens of megabits. Applications are microcontrollers, baseband and media processors, multi-RF, wireless LAN and more

 The diagram above shows how the programming works. There are two transistors per cell. The top one remains a transistor for a 0 (gate isolated from the source/drain) but after programming a 1 the oxide is punched through and the gate has a high resistance short to the drain. Since the actual damage to the gate oxide might occur anywhere (close to the drain or far from it), the resulting resistance is variable.

The traditional way to read the data is as follows. The bitline (WLP) is pre-charged, then the appropriate wordline (WLR) is used for access and the bitline (BL) is sensed and compared against a reference in the sense amp. Depending on whether the “transistor” is a transistor or a resistor, the current will be higher than the reference bitline current or not. If it is higher then a 1 is sensed, lower and a zero. The challenge is to sense the data fast, since the longer the time taken, the clearer the value, but all users want a fast read time. See the diagram below.
 Historically this has worked well. In older nodes, the variations are small relative to the drive strengths of the transistors. But increasingly it gets harder to tell the difference between a weak 1 cell and an noisy 0 cell, which risks misreading the value. As a result it can take a long time to sense “to be sure.” As we march down the treadmill of process nodes, like many other things, the variation is getting so large it is approaching the parameters of the device itself. A new approach is needed.
 The new approach the Kilopass have pioneered adds a couple of steps. Once the word line is used for access, after a delay the bitline reference is shut off. The bit line is sensed and the data latched and then the sense amp is shut off. The new sense amp incorporates the timing circuitry. The whole scheme is more tolerant of process variation and should be suitable for migration all the way to below 10nm. This approach is more immune to ground noise and has greater discrimination between weak 1 and noisy 0. Finally, shutting off the sense amp at the end saves power.
 It turns out that this scheme works particularly well with TSMC’s process since their I[SUB]ref[/SUB] spread is half that of other fabs. The new sensing scheme coupled with tighter cell means doubling the read speed.

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