Creating Reliable Memory Interfaces Fast and Easy

Creating Reliable Memory Interfaces Fast and Easy
by Admin on 10-13-2022 at 10:00 am

Part of Keysight’s ‘Simulating for High-Speed Digital Insights’ webinar series

October 13, 2022 | 10:00 AM PT / 1:00 PM ET

Successful memory interface design is more than building and simulating one design that works to the given specification. As a designer, your success relies on making a robust implementation… Read More


Flash Memory Summit Conference

Flash Memory Summit Conference
by Admin on 08-02-2022 at 12:00 am

Why Attend Flash Memory Summit?

FMS is the best networking opportunity in the storage industry!

The 2022 conference is expanding beyond flash memory to address all forms of high performance memory. Summit organizers welcome your submissions on a range of memory technologies including NAND Flash, DRAM, MRAM, ReRAM, and DNA storage.… Read More


Analyzing Memory Bus to Meet with DDR Specifications

Analyzing Memory Bus to Meet with DDR Specifications
by Admin on 04-14-2022 at 10:00 am

Part of Simulating for High-Speed Digital Insights series

April 14, 2022 | 10:00 AM PT / 1:00 PM ET

Due to ever increasing data demand, the speed grade for memory is now in the multi-gigabit range. Memory bus design becomes a lot more complicated with tighter design margins due to higher crosstalk between vias and traces along with… Read More


Memory Bandwidth Races Higher with HBM3

Memory Bandwidth Races Higher with HBM3
by Admin on 03-15-2022 at 12:00 am

March 15th @ 11am PT | 2pm ET

With the formal release of the HBM3 specification, memory bandwidth for AI/ML and HPC shifts to a higher gear. Terabytes of bandwidth are possible using HBM3’s 2.5D/3D architecture. Join memory expert Frank Ferro as he discusses what changes come with the new generation of HBM, and how the Rambus HBM3

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How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance

How Synopsys Interface IP and Arm Interoperate to Accelerate System IO and Memory Performance
by Admin on 09-15-2021 at 12:00 am

In this webinar, Synopsys and Arm describe how their recent collaboration helps maximize system performance and shorten Arm-based SoC design cycles. Learn how to minimize HPC/data center SoC design risk and ensure end-to-end IP integration, using available Arm reference designs and interoperability reports. Find out how… Read More


Can Threshold Switches Replace Transistors in the Memory Cell?

Can Threshold Switches Replace Transistors in the Memory Cell?
by Fred Chen on 06-08-2020 at 6:00 am

Threshold switch I V

The overwhelming majority of transistors produced in the world are used in memory cells, either as the memory itself (Flash, SRAM), or as the access device (DRAM). Yet, it is not necessary to have a transistor in every memory cell. In 2015, 3D XPoint, the first major product based on transistor-less memory cells, was announced [1].

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Lithography Resolution Limits – Arrayed Features

Lithography Resolution Limits – Arrayed Features
by Fred Chen on 04-17-2020 at 6:00 am

Lithography Resolution Limits Arrayed Features

State-of-the-art chips will always include some portions which are memory arrays, which also happen to be the densest portions of the chip. Arrayed features are the main targets for lithography evaluation, as the feature pitch is well-defined, and is directly linked to the cost scaling (more features per wafer) from generation… Read More


Webinar – AI/ML SoC Memory and Interconnect IP Perspectives

Webinar – AI/ML SoC Memory and Interconnect IP Perspectives
by Tom Simon on 10-08-2019 at 10:00 am

For decades development work on Artificial Intelligence (AI) and Machine Learning (ML) was done on traditional CPUs and memory configurations. Now that we are in the “hockey stick” upturn in deployment of AI and ML, the search is on for the most efficient types of processing architectures. The result is a wave of development for… Read More


Low Power SRAM Complier and Characterization Enable IoT Applications

Low Power SRAM Complier and Characterization Enable IoT Applications
by Tom Simon on 02-22-2019 at 7:00 am

If you are designing an SOC for an IoT application and looking to minimize power consumption, there are a lot of choices. However, more often than not, looking at reducing SRAM power is a good place to start. SRAMs can consume up to 70% of an IC’s power. SureCore, a leading memory IP supplier, offers highly optimized SRAM instances … Read More


SOC security is not a job for general purpose CPUs

SOC security is not a job for general purpose CPUs
by Tom Simon on 01-14-2019 at 7:00 am

Life is full of convenience-security tradeoffs. Sometimes these are explicit, where you get to make an active choice about how secure or insecure you want things to be. Other times we are unaware of the choices we are making, and how risky they are for the convenience provided. If you leave your bike unlocked, you can expect it to be… Read More