Low Power SRAM Complier and Characterization Enable IoT Applications

Low Power SRAM Complier and Characterization Enable IoT Applications
by Tom Simon on 02-22-2019 at 7:00 am
Categories: IoT, IP, sureCore

If you are designing an SOC for an IoT application and looking to minimize power consumption, there are a lot of choices. However, more often than not, looking at reducing SRAM power is a good place to start. SRAMs can consume up to 70% of an IC’s power. SureCore, a leading memory IP supplier, offers highly optimized SRAM instances … Read More

June 5, 2018

Imec technology forum 2018 – the future of memory

Imec technology forum 2018 – the future of memory
by Scotten Jones on 06-05-2018 at 12:00 pm
Categories: Events, FinFET, Foundries
1 Comment

At the Imec technology forum in Belgium Gouri Sankar Kar and Arnaud Furnemont presented memory and storage perspectives and I also got to interview Arnaud. Arnaud leads overall memory development at Imec and personally leads NAND and DNA research.

Memory research is focused on power, energy, speed and cost with energy and throughput… Read More

April 18, 2018

Artificial Intelligence calls for Smart Interconnect

Artificial Intelligence calls for Smart Interconnect
by Tom Simon on 04-18-2018 at 7:00 am
Categories: AI, EDA, IP, NetSpeed Systems

Artificial Intelligence based systems are driving a metamorphosis in computing, and consequently precipitating a large shift in SOC design. AI training is often done in the cloud and has requirements for handling huge amounts of data with forward and backward data connections. Inference usually occurs at the edge and must be… Read More

October 30, 2017November 22, 2019

The perfect pairing of SOCs and embedded FPGA IP

The perfect pairing of SOCs and embedded FPGA IP
by Tom Simon on 10-30-2017 at 12:00 pm
Categories: Achronix, eFPGA, Events, FPGA, IP

In life, there are some things that just go together. Imagine the world without peanut butter and jelly, eggs and potatoes, telephones and voicemail, or the internet and search engines. In the world of computing there are many such examples – UARTS and FIFO’s, processor cores and GPU’s, etc. Another trait all these things have is… Read More

September 19, 2017June 14, 2019

Improved Memory Design, Characterization and Verification

Improved Memory Design, Characterization and Verification
by Daniel Payne on 09-19-2017 at 12:00 pm
Categories: Cadence, EDA, FinFET

My IC design career started out with DRAM design, characterization and verification back in the 1970’s, so I vividly recall how much SPICE circuit simulation was involved, and how little automation we had back in the day, so we tended to cobble together our own scripts to help automate the process a bit. With each new process… Read More

August 22, 2017June 14, 2019

HBM offers SOC’s dense and fast memory options

HBM offers SOC’s dense and fast memory options
by Tom Simon on 08-22-2017 at 7:00 am
Categories: IP, Synopsys

Dual in-line memory modules (DIMM’s ) with double data rate synchronous dynamic random access memory (DDR SDRAM) have been around since before we were worried about Y2K. Over the intervening years this format for provisioning memory has evolved from supporting DDR around 1995, to DDR1 in 2000, DDR2 in 2003, DDR4 in 2007 and DDR4… Read More

June 29, 2017

Memories for the Internet

Memories for the Internet
by Tom Simon on 06-29-2017 at 12:00 pm
Categories: eSilicon, IP, Semiconductor Services
8 Comments

In 1969 the Internet was born at UCLA when a computer there sent a message to a computer at Stanford. By 1975, there were 57 computers on the ‘internet’. Interestingly in the early seventies I actually used the original Xerox Sigma 7 connected to the internet in Boelter Hall at UCLA. A similar vintage computer is now in this room commemorating… Read More

April 6, 2017June 14, 2019

Machine Learning Accelerates Library Characterization by 50 Percent!

Machine Learning Accelerates Library Characterization by 50 Percent!
by Daniel Nenni on 04-06-2017 at 7:00 am
Categories: EDA, Solido

Standard cell, memory, and I/O library characterization is a necessary, but time-consuming, resource intensive, and error-prone process. With the added complexity of advanced and low power manufacturing processes, fast and accurate statistical and non-statistical characterization is challenging, creating the need … Read More

November 4, 2016

RRAM Redux

RRAM Redux
by Bernard Murphy on 11-04-2016 at 7:00 am
Categories: IP

Advanced memory technologies are a perennially hot topic thanks to a proliferation of data-hungry applications pushing our demand for more capacity and performance at less power and area. Among several technology contenders is Resistive RAM or RRAM (also called ReRAM). In this technology a conducting filament is grown through… Read More

September 10, 2016June 14, 2019

TSMC and Solido to Share Experiences with Managing Variation in Webinar

TSMC and Solido to Share Experiences with Managing Variation in Webinar
by Tom Simon on 09-10-2016 at 7:00 am
Categories: EDA, Foundries, Solido, Synopsys, TSMC

TSMC knows better than anyone the effect that variation can have at advanced process nodes. Particularly in memory designs and in standard cell designs, variation has become a very critical because of its effects on yield and because of the high-cost of compensating for it. Smaller feature sizes combined with lower voltage thresholds… Read More

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