Synopsys have been gradually broadening their portfolio of verification IP (VIP). It is 100% native SystemVerilog with native debug using Verdi (that was acquired from SpringSoft last year, now fully integrated into Verification Compiler). It has native performance with VCS. Going forward there are source code test suites.… Read More
There is never enough memory bandwidth. Well, occasionally there is but many SoCs have lots of blocks that communicate through memory, typically off-chip DRAM. In 2001 Sonics created their first solution to this problem with MemMax technology that was incorporated into their SonicsSX product. This has been used in over 100 designs… Read More
One of Coventor’s flagship products is SEMulator3D, and at Semicon West they announced a new version, 2014.100.
SEMulator3D is a powerful 3D semiconductor and MEMS process modeling platform. It uses highly efficient physics-driven voxel modeling technology. It models the physical effects of process steps, which is… Read More
When people discuss capabilities of leading edge process nodes they tend to focus on digital logic. Microprocessors in particular. But a process requires more than just digital logic and standard cells to be successful. In particular, pretty much every SoC contains a lot of memory so the memory capabilities of a process are important.… Read More
eMMC is the standard for mobile memory used in smartphones and tablets. The latest standard, released just this year, is eMMC 5.0. The previous standard, 4.51, was only released last year so things are moving quickly.
Arasan have a webinar next week to bring you up to speed on eMMC 5.0 in general and, of course, their own IP offering… Read More
The GSA Memory+ conference Taiwan will take place on (Halloween!) October 31, 2013 at the Regent Taipei, Taiwan. The main theme of this year is highlighting Memory—the Critical Enabler for Prominent and Emerging Applications in System Logic Solutions.
GSA Memory+ Conference is the global industry event dedicated to all memory… Read More
Today Micron announced that it is shipping 2GB Hybrid Memory Cube (HMC) samples. The HMC is actually 5 stacked die connected with through-silicon-vias (TSVs). The bottom die is a logic chip and is actually manufactured for Micron in an IBM 32nm process (and doesn’t have any TSVs). The other 4 die are 4Gb DRAM die manufactured… Read More
Lately I was studying about new innovations in memory world such as ReRAM and Memristor. As DRAM (although it has become a commodity) has found its extensive use in mobile, PC, tablet and so on, that was an inclination too to know more about. While reviewing Cadence’s offering in memory subsystems, I came across this whitepaperwhich… Read More
All chips have critical power management requirements, often with multiple supply voltages. Digital power management ICs (PMICs) are commonplace to convert unregulated voltages from batteries and noisy power supplies to fully regulated accurate power to keep even the most sensitive chips performing.
Powervation is a company… Read More
It was a nice break after my vacation, indulging into some of the pure science stuff, when an old colleague of mine, Dr. Gaurav Gandhi, founder of mLabs in Delhi came across introducing me to his new research and possible developments in this field. Gaurav was actually in my product validation team while I was at Cadence, very passionate… Read More
