Webinar: Fast-track SoC Verification – Reduce time-to-first-test with Synopsys VC AutoTestbench

Webinar: Fast-track SoC Verification – Reduce time-to-first-test with Synopsys VC AutoTestbench
by Bernard Murphy on 01-25-2018 at 7:00 am

There seems to be a general sense that we have the foundations for block/IP verification more or less under control, thanks to UVM standardizing infrastructure for directed and constrained-random testing, along with class libraries providing building blocks to simplify verification reuse, build sequence tests, verify register… Read More


Up front phases improve CDC analysis

Up front phases improve CDC analysis
by Don Dingee on 09-19-2016 at 4:00 pm

Many tools find clock domain crossings (CDCs) in FPGA designs. Some don’t find the right ones since they don’t comprehend things like in-house synchronizer constructs. Some find too many based on misunderstanding intent, inaccurate constraints, and other factors that lead to noise.… Read More


Market Trends Motivate a Shift-Left in Functional Verification

Market Trends Motivate a Shift-Left in Functional Verification
by Jean-Marie Brunet on 09-15-2016 at 4:00 pm

Today, in the context of functional verification, industry trends are based on the needs of prominent vertical markets. There is some overlap in what these markets need, but there are some use models that are very specific to each market.

We assert this because we have a lot of customers asking about emulation solutions not from … Read More


Pseudo random generator tutorial in VHDL (Part 3/3)

Pseudo random generator tutorial in VHDL (Part 3/3)
by Claudio Avi Chami on 09-04-2016 at 4:00 pm



On the first two chapters of this Tutorial we started with a simple LFSR module and added a test bench. Then, on chapters three and four we upgraded our module with some features and learned to export the test bench data to files.
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Striving for one code base in accelerated testbenches

Striving for one code base in accelerated testbenches
by Don Dingee on 08-26-2016 at 4:00 pm

Teams buy HDL simulation for best bang for the buck. Teams buy hardware emulation for the speed. We’ve talked previously about SCE-MI transactors as a standardized vehicle to connect the two approaches to get the benefits of both in an accelerated testbench – what else should be accounted for?… Read More


Optimization and verification wins in IoT designs

Optimization and verification wins in IoT designs
by Don Dingee on 08-17-2016 at 4:00 pm

Designers tend to put tons of energy into pre-silicon verification of SoCs, with millions of dollars on the line if a piece of silicon fails due to a design flaw. Are programmable logic designers, particularly those working with an SoC such as the Xilinx Zynq, flirting with danger by not putting enough effort into verification?… Read More


Aldec extends FPGA and ASIC flows at DAC

Aldec extends FPGA and ASIC flows at DAC
by Don Dingee on 05-20-2016 at 4:00 pm

Aldec tools and services have long been associated with FPGA designs. As FPGAs have evolved toward more RTL-based designs, the similarities between a modern FPGA verification flow and an ASIC verification flow often leave them looking virtually the same. … Read More


Fastest SoC time-to-success: emulators, or FPGA-based prototypes?

Fastest SoC time-to-success: emulators, or FPGA-based prototypes?
by Don Dingee on 02-11-2016 at 12:00 pm

Hardware emulators and FPGA-based prototyping systems are descendants of the same ancestor. The Quickturn Systems Rapid Prototype Machine (RPM) introduced in May 1988 brought an array of Xilinx XC3090 FPGAs to emulate designs with hundreds of thousands of gates. From there, hardware emulators and FPGA-based prototyping … Read More