Sigasi at the 2024 Design Automation Conference

Sigasi at the 2024 Design Automation Conference
by Daniel Nenni on 06-20-2024 at 2:00 pm

DAC 2024 Banner

Sigasi® will demonstrate its Sigasi Visual HDL™ (SVH™) portfolio during DAC, showing how it supports the shift-left methodology for chip design, catching specification errors early in the design cycle and fixing the inefficient HDL-based design flow.

The traditional HDL workflow cannot accommodate the massive amounts of… Read More


Continuous Integration of UVM Testbenches

Continuous Integration of UVM Testbenches
by Daniel Nenni on 09-13-2021 at 6:00 am

UVM Report

In recent years, one of the hot topics in chip design and verification has been continuous integration (CI). Like many innovations in hardware development, it was borrowed from software engineering and the programming world. The concept is simple: all code changes from all developers are merged back into the main development… Read More


Life in a Formal Verification Lane

Life in a Formal Verification Lane
by Shinavi Shah on 06-22-2021 at 6:00 am

New image for semiwiki

This summer, I got the opportunity to work as a Formal Verification Intern with Axiomise for six weeks. I’m a keen designer and love working in design and architecture. Although, I’ve not started my professional career yet, I have done most of my projects as a designer in my undergraduate and postgraduate studies.

Having said that,… Read More


Webinar: Static Verification for RISC-V Cores and SoCs

Webinar: Static Verification for RISC-V Cores and SoCs
by Daniel Nenni on 09-28-2020 at 6:00 am

Aldec RISC V Webinar SemiWiki 1

RISC-V has been trending ever since it landed on SemiWiki in 2016.  Even more so now that Arm is in flux with the Nvidia acquisition. Verification is a fast growing EDA challenge with the number of verification engineers steadily outpacing design, so this webinar is a best case scenario for SemiWiki traffic, absolutely.

Two thingsRead More


WEBINAR: UVM RISC-V and DV

WEBINAR: UVM RISC-V and DV
by Daniel Payne on 09-21-2020 at 10:00 am

UVM Testbench RISC-V

Oh, our semiconductor industry just loves acronyms, and the title of my blog packs three of the most popular acronyms together at once. I attended a webinar hosted by Aldec last week on this topic, “UVM Simulation-based environment for Ibex RISC-V CPU core with Google RISC-V DV“. Verification engineers have been … Read More


Automobility: The Bot in a Box Boom

Automobility: The Bot in a Box Boom
by Roger C. Lanctot on 11-20-2016 at 4:00 pm

The Automobility event, which starts today ahead of the Los Angeles Auto Show, will be remembered for introducing the bot in a box. While Ford Motor Company President and CEO Mark Fields will take the stage this morning to tout Ford’s leadership in transforming transportation with new vehicle ownership models and mass produced… Read More


DDoS Attack: A Wake-Up Call for IoT

DDoS Attack: A Wake-Up Call for IoT
by Ahmed Banafa on 11-13-2016 at 12:00 pm

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Welcome to the world of Internet of Things wherein a glut of devices are connected to the internet which emanates massive amounts of data. Analysis and use of this data will have real positive impact on our lives. But we have many hoops to jump before we can claim that crown starting with a huge number of devices lacking unified platform… Read More


Vlang – Opportunities Galore for Productivity & Performance

Vlang – Opportunities Galore for Productivity & Performance
by Pawan Fangaria on 08-19-2014 at 2:01 pm

Yes, verification technologies are open to innovation for improved productivity and performance in the face of ever growing SoC/IP design sizes and complexities. There is not much scope left in processor speed to improve, other than multi-core processors in servers which again need software properly architected to be thread-able… Read More


The Future of Money is Digital – Part 2

The Future of Money is Digital – Part 2
by Sam Beal on 02-23-2014 at 11:30 am

BitCoin Algorithm
Invented by a mystery person/group with the alias “Satoshi Nakamoto”. [You can read a consolidation of the paper here]. The essential elements are:

· Peer to Peer Network with self-validation
· Exponentially increasing compute cost
· Finite supply with exponential conversion
· Hidden in plain… Read More