Yes, verification technologies are open to innovation for improved productivity and performance in the face of ever growing SoC/IP design sizes and complexities. There is not much scope left in processor speed to improve, other than multi-core processors in servers which again need software properly architected to be thread-able and scalable to speed up the simulation run. So, where are the opportunities? The hidden secret is that there are many programming features, styles, verification features, compiler technologies and other performance enablers which can be manifested into the hardware design & verification languages and exploited to improve performance of simulation and productivity of design and test infrastructure development.
Since there is ample scope of improvement in the design of a hardware description language from productivity and performance standpoint, we regularly see new languages coming up, often subverted by standardization paradigm, leaving divided choices for designers to choose one over the other – standard language or more powerful language. Today we have Verilog, VHDL, SystemVerilog, SystemC, SpecC, SystemRDL, ‘e’, and many others, usually the powerful ones are not widely heard but used by designers and developers internally; they switch to standard ones when interoperability is needed. I need not mention there are smart SoC/IP vendors who use their proprietary languages/compilers for faster verification.
Coming to Vlang, what is this new incarnation? This is a new powerful hardware verification language, derived from the powerful open source language ‘D’. This is a language which appears to have best of both worlds; while it enhances the power of verification by several means, it retains ease of generic programming, clean syntax and semantics, safety and object oriented methodology like a standard language. The result is a powerful language with high performance and high productivity that enables designers and verification engineers to start early and gain higher verification coverage faster.
Vlang is ABI (Application Binary Interface) compatible that provides much better integration with C++ compared to SystemVerilog which is limited to C with DPI (Direct Programming Interface) resulting into inefficiency in any interface between SystemVerilog and SystemC. What is important is that any method (including virtual methods) on C++ objects can be called directly from Vlang without the need of any boilerplate code. These advantages make Vlang ideal for any ESL model verification and also for creating high performance testbenches for driving emulation platforms.
Let’s look at some of the key performance features of Vlang. It’s uniquely architected to support full blown multi-core concurrency to take advantage of multi-core processor architecture. The concurrency is available at any convenient abstraction level that can be effectively scaled for VIPs. The language supports excellent, state-of-science compile time with less code generation (without any need of boilerplate code) that compiles at lightning speed and simulates faster. It can support multiple simulators in single simulation with excellent simulation management. It supports fast and advanced constrained randomization that takes lesser simulation time.
From the productivity standpoint, it provides high productivity matrix with clean and easy syntax to quickly learn and program, high degree of reusability with true object orientation, generic programming, template meta-programming and concepts, automatic garbage collection like any other modern language does, and UVM Standard 1.1d support with multi-core concurrent and parallel, many uvm_root instantiations.
A good aspect of Vlang is that it is free and open source. I admire open source because it’s the source of innovation with dedicated user force. Of course there can be concerns about supportability of a version for a long time, but reliable partners shouldn’t disappoint you.
Vlang is developed and maintained by Puneet Goel. He can be reached at email@example.com.