Webinar: Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning

Webinar: Questa RDC Assist – Improving designer productivity and enabling faster RDC verification closure with machine learning
by Admin on 05-10-2024 at 2:41 pm

In 2021 Siemens EDA released CDC Assist.  CDC Assist is an ML powered feature that empowers users to configure, debug, and close CDC on designs more rapidly. Following the success of CDC Assist, Siemens introduced RDC Assist in 2023.

Using the same ML technology in CDC Assist, RDC Assist dramatically improves the time and effort

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Webinar: New Advanced Techniques for Reset Domain Crossing (RDC) Analysis

Webinar: New Advanced Techniques for Reset Domain Crossing (RDC) Analysis
by Admin on 02-26-2024 at 7:58 pm

About

Designers increasingly use complex reset signaling architectures to meet high-performance, low-latency, and low-power requirements. Specifically, independent reset domains are created by complex reset sequences, reset circuitry, and the intermixing of IPs with different reset schemas, power-management domains,Read More


CDC Workshop: “Hierarchical CDC and RDC Closure with Standard Abstract Models”

CDC Workshop: “Hierarchical CDC and RDC Closure with Standard Abstract Models”
by Admin on 02-20-2024 at 4:07 pm

Accellera at DVCon US 2024

Abstract:

As complexity and the number of clock domains increase in today’s ASIC designs, we are moving towards a hierarchical verification approach. This tutorial covers the proven clock domain crossings (CDC) and Reset Domain Crossing (RDC) schemes, the verification challenges, and the potential… Read More


Webinar: Comprehensive Static Verification for FPGA and ASIC RTL Designers

Webinar: Comprehensive Static Verification for FPGA and ASIC RTL Designers
by Admin on 06-20-2023 at 4:18 pm

As designs get increasingly complex, design teams are looking to find bugs earlier, to reduce rework and shorten time-to-market. The ultimate “shift left” is to put easy-to-use static verification in the hands of RTL designers to eliminate bugs at their source.

This webinar covers comprehensive static verification capabilities… Read More


Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis

Constraints-Driven CDC and RDC Verification Including UPF Aware Analysis
by Admin on 06-13-2022 at 1:48 pm

Synopsys Webinar | Thursday, June 23, 2022 | 10:00 – 11:00 a.m. Pacific

Today’s million gates integrated circuits (ICs) involve various intellectual properties (IPs) interfacing with each other through multiple asynchronous clock and reset domains. Ensuring all clocks propagate concurrently across each clock tree

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Getting to Faster Closure through AI/ML, DVCon Keynote

Getting to Faster Closure through AI/ML, DVCon Keynote
by Bernard Murphy on 03-10-2022 at 10:00 am

Manish min

Manish Pandey, VP R&D and Fellow at Synopsys, gave the keynote this year. His thesis is that given the relentless growth of system complexity, now amplified by multi-chiplet systems, we must move the verification efficiency needle significantly. In this world we need more than incremental advances in performance. We need… Read More


Automotive SoCs Need Reset Domain Crossing Checks

Automotive SoCs Need Reset Domain Crossing Checks
by Tom Simon on 01-19-2021 at 6:00 am

reset domain crossing verification

When the number of clock domain crossings (CDCs) in SoCs proliferated it readily became apparent that traditional verification methods were not well suited to ensuring that they were properly handled in the design. This led to the creation of new methods and tools to check for correct interfaces between domains. Now, in automotive… Read More


Structural CDC Analysis Signoff? Think Again.

Structural CDC Analysis Signoff? Think Again.
by Bernard Murphy on 08-05-2020 at 6:00 am

strainer min

Talking not so long ago to a friend from my Atrenta days, I learned that the great majority of design teams still run purely structural CDC analysis. You should sure asynchronous clock domains are suitably represented in the SDC, find all places where data crosses between those domains that require a synchronizer, gray-coded FIFO… Read More


Design Perspectives on Intermittent Faults

Design Perspectives on Intermittent Faults
by Bernard Murphy on 10-08-2019 at 5:00 am

Faults

Bugs are an inescapable reality in any but the most trivial designs and usually trace back to very deterministic causes – a misunderstanding of the intended spec or an incompletely thought-through implementation of some feature, either way leading to reliably reproducible failure under the right circumstances. You run diagnostics,… Read More


RDC – A Cousin To CDC

RDC – A Cousin To CDC
by Alex Tan on 04-18-2018 at 12:00 pm

In a post-silicon bringup, it is customary to bring the design into a known state prior to applying further testing sequences. This is achieved through a Power-on-Reset (POR) or similar reset strategy which translates to initializing all the storage elements to a known state.

During design implementation, varying degrees of… Read More