Design Perspectives on Intermittent Faults

Design Perspectives on Intermittent Faults
by Bernard Murphy on 10-08-2019 at 5:00 am

Bugs are an inescapable reality in any but the most trivial designs and usually trace back to very deterministic causes – a misunderstanding of the intended spec or an incompletely thought-through implementation of some feature, either way leading to reliably reproducible failure under the right circumstances. You run diagnostics,… Read More


RDC – A Cousin To CDC

RDC – A Cousin To CDC
by Alex Tan on 04-18-2018 at 12:00 pm

Image RemovedIn a post-silicon bringup, it is customary to bring the design into a known state prior to applying further testing sequences. This is achieved through a Power-on-Reset (POR) or similar reset strategy which translates to initializing all the storage elements to a known state.

During design implementation, varying… Read More


Caution: Reset Domains Crossing

Caution: Reset Domains Crossing
by Bernard Murphy on 04-01-2017 at 7:00 am

Because you can never have too much to worry about in verification, reset domain crossings (RDCs) are Image Removedanother hazard lying in wait to derail your design. Which hardly seems fair. We like to think of resets as dependable anchors to get us back on track when all else fails, but it seems their dependability is not absolute,… Read More


Domain Crossing Verification Needs Continue to Grow

Domain Crossing Verification Needs Continue to Grow
by Bernard Murphy on 01-29-2016 at 4:00 pm

Clock domain crossing (CDC) analysis has been around for many years, initially as special checksImage Removed in verification or static timing analysis, but it fairly quickly diverged into specialized tools focused just on this problem. CDC checks are important because (a) you can lose data or even lock up at, or downstream of… Read More