The speed and power penalties for accessing system RAM affect everything from artificial intelligence platforms to IoT sensor nodes. There is a huge power and performance overhead when the various IP blocks in an SOC need to go to DRAM. Memory caches have become essential to SOC design to reduce these adverse effects. However, ensuring cache coherency across all the local caches and system RAM can be tricky. The problem was not so bad when there were fewer IP’s that required caches, but things have changed.
Up until now, cache coherency solutions were typically manually created for point to point connections to DRAM or specific IP existed for cache coherency to serve predetermined use models. However, it looks like Arteris has announced what might be game changing technology for implementing cache coherent systems on a wide range of SOC’s. Their announcement on May 17[SUP]th[/SUP] states that the technology can be used to connect a large variety of IP, including those with differing cache coherency protocols, semantics and sizes. It can even be configured to provide the benefits of caching to IP blocks that do not support local caches.
It’s expected that Arteris will offer more details about the technology and its implementation in the coming weeks. Nonetheless, a lot can be gleaned from the recent announcement. First and foremost, it’s apparent that Arteris is using their robust and proven FlexNoC on-chip interconnect IP as a building block for this technology. Arteris is already adept at moving data around on SOC’s, where the data sizes and protocols vary dramatically. It makes complete sense to take advantage of this transport technology to help implement interfaces for cache agents.
According to their announcement, the new technology can simultaneously support heterogeneous cache agents, and even easily add local coherent caches to non-cache IP’s. This should make it easy to mix IP’s from different sources. Arteris offers the capability to add proxy caches to non caching clients to boost overall system performance. These proxy caches will fully participate in the coherency management process.
Another key element of the technology is the availability of multiple configurable snoop filters. By customizing the organization, size and associativity of multiple snoop filters SOC designers can improve the PPA of their designs.
This Arteris technology is scalable and configurable. Each cache agent can be configured to suit its own needs and to talk to the other members of the coherency system by using optimal interfaces. By using FlexNoC as its transport layer brings all the FlexNoC advantages to the implementation. Typical design concerns are area for interconnect resources, timing and power consumption.
One of the core tenets of the Ateris team is that ‘wires’ are very expensive relative to the cost of transistors in advanced nodes. This counterintuitive sounding assertion comes from looking at total system area needed for point to point interconnect. Very complex IP blocks typically need to talk to many other subsystems. Wiring up dedicated connections for all the subsystem that need to talk to each other would be prohibitive. Even if the blocks were connected this way, we would see that the utilization would be pretty low. Just as FlexNoC improves data transfer between blocks, it can be used as a building block for cache coherency. The same benefits apply – optimal utilization of system resources, configurability, etc.
With this technology Arteris is now offering unique enabling technology that is not available anywhere else. Nevertheless, it is compatible with coherency offerings from ARM and others. For Arteris, it shows a unique level of innovation and a willingness to go deeper into the design process to develop new products that solve significant design problems.