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Aldec Swings for the Fences

Aldec Swings for the Fences
by Bernard Murphy on 03-17-2017 at 7:00 am

In today’s fast-moving technology markets, companies who are prepared to step up to opportunity can break  out of traditional bounds to become players in bigger and fast-growing markets. It looks to me like Aldec is putting itself on that path. They have announced an end-to-end hardware/software co-verification solution which they showed at Embedded World in Nuremberg recently.

The solution starts with linkage to a QEMU ARM emulation linked directly to HDL running on the Aldec Riviera-PRO simulator. Being a techie myself, I’m guessing other techies are going to say “but that’s not a big deal – others have virtual prototypes linked to simulators”. But business breakthroughs are usually not predicated on major technical leaps. It’s more important that they target hot problems with workable solutions, most often integrated around existing capabilities. Aldec’s also has a unique advantage here in their design for FPGA focus.

The solution currently targets Xilinx Zynq SoCs with dual ARM Cortex A9. As you know if you read the Mentor survey on functional verification, advanced verification methods are becoming much more common on these complex FPGA SoCs, where traditional “burn and churn” verification approaches have become impractical. So logic simulation coupled with QEMU system emulation is a very practical solution to managing hardware/software co-development. Hardware breakpoints can be set in Riviera-PRO, software breakpoints can be set through QEMU and concurrent debug can be managed through GDB and Riviera-PRO.

At the show, Aldec provided insight into using the solution to model the ARM core running in QEMU, together with a MIPI CSI-2 solution running in the FPGA. But Aldec didn’t stop there. They also showed off three reference designs designed using this flow and built on their TySOM boards.

The first reference design targets multi-camera surround view for ADAS (automotive – advanced driver assistance systems). Camera inputs come from four First Sensor Blue Eagle systems, which must be processed simultaneously in real-time. A lot of this is handled in software running on the Zynq ARM cores but the computationally-intensive work, including edge detection, colorspace conversion and frame-merging, is handled in the FPGA. ADAS is one of the hottest areas in the market and likely to get hotter since Intel just acquired Mobileye.

The next reference design targets IoT gateways – also hot. Cloud interface, through protocols like MQTT, is handled by the processors. The gateway supports connection to edge devices using wireless and wired protocols including Bluetooth, ZigBee, Wi-Fi and USB.

Face detection for building security, device access and identifying evil-doers is also growing fast. The third reference design is targeted at this application, using similar capabilities to those on the ADAS board, but here managing real-time streaming video as 1280×720 at 30 frames per second, from an HDR-CMOS image sensor.

So yes, Aldec put together a solution combining their simulator with QEMU emulation and perhaps that wouldn’t justify a technical paper in DVCon. But business-wise they look like they are starting on a much bigger path. They’re enabling FPGA-based system prototype and build in some of the hottest areas in systems today and they make these solutions affordable for design teams with much more constrained budgets than are available to the leaders in these fields. And they provide reference boards with embedded development kits to get those teams started in ADAS, IoT gateway and face recognition systems. That looks to me like a swing for the fences.

You can read the press release HERE.

More articles by Bernard…


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