The TSMC Symposium was jam-packed this year with both people and information. I had another 60 minutes of fame in the Solido booth where I signed 100 books, thank you to all who stopped by for a free book and a SemiWiki pen. SemiWiki bloggers Tom Dillinger and Tom Simon were also there so look for more TSMC Symposium blogs coming in the next few days. If you have specific questions ask them here and I will make sure you get answers.
Rick Cassidy, President, TSMC North America again kicked of the conference with a nice overview of the semiconductor business. In fact, TSMC shipped 5.8M (12” equiv) wafers in 2016 to more than 450 customers with 5,238 products. Approximately 71% of the resulting revenue went through Rick and the TSMC North American organization so congratulations to them on a job well done.
One of the reoccurring points made by Rick and the other TSMC executives is that TSMC does not compete with their customers which is the foundation of the pure-play foundry business and the key to the success of the fabless semiconductor industry, absolutely.
This year TSMC really focused on custom process platforms for key market segments of the semiconductor industry. I went into a bit more detail on this in my pre-symposium blog TSMC Design Platforms Driving Next-Gen Applications. That blog went viral with more than 10,000 views in one week so you may want to check it out.
There were three big announcements yesterday in my opinion:
1. 22nm ULP
2. 12nm FFC
3. 7nm EUV
Most of us had advanced knowledge of this but it was nice to hear more details in front of more than 1,000 TSMC customers. Again, this is an invitation only event with no recording or photography allowed so much more information is made available than open events or conferences.
TSMC formally introduced 22nm ULP (an optimized version of 28nm HPC+) and 12nm FFC (an optimized version of 16nm). 22nm ULP offers a 10% area reduction and either a 15% performance gain over 28nm or a 35% power reduction. TSMC also has 55nm ULP, 40nm ULP, and 28nm ULP all targeted at IoT and other low power and low cost applications. 12nm FFC offers a 10% performance gain or a 25% power reduction. 12nm also offers a 20% area reduction with 6T Libraries versus 7.5T or 9T.
TSMC 10nm is now fully qualified and in HVM at Giga Fabs 12 and 15. TSMC is scheduled to ship 400,000 wafers in 2017 so you can expect the next Apple iProducts to sport TSMC 10nm SoCs, definitely.
Other than that, 10nm was not discussed much because it is another short node like 20nm. Remember, TSMC introduced double patterning at 20nm then quickly followed with FinFETs at 16nm. This proved to be very a wise approach since the same fabs were used for both 20nm and 16nm which simplified the 16nm ramp. We will see the same with 10nm and 7nm. TSMC ramped 10nm without quad patterning and will add it with 7nm, again using the same fabs.
7nm was the focus of the technical discussions of course because it represents several firsts for our industry. 7nm will also represent the biggest market share for TSMC for one node, second being 28nm I believe. It would be easier to count the big semiconductor companies that are NOT using TSMC 7nm and the only two I can think of are Samsung and Intel.
In comparison to 16FF+, TSMC 7nm is said to offer a 3.3x density, 30% speed, and a 60% power improvement. TSMC will again offer multiple versions of 7nm for platform specific applications (Mobile, IoT, AI, and Automotive). The 7nm SRAM bit cell is .37x compared to 16nm which I believe will be the smallest SRAM bit cell in production so congratulations to the SRAM team in Hsinchu. 7nm will hit risk production in April and HVM in the first half of 2018, and yes, next year’s iProducts will sport TSMC 7nm SoCs.
The big shocker to me was that TSMC is still committed to introducing EUV at 7nm in 2019. Based on what I saw at the SPIE conference last month EUV would miss 7nm completely. This will be another first for the industry (EUV in production) so I can see the incentive but I highly doubt the ROI will be there at 7nm.
TSMC also stated that 5nm development is progressing according to plan with good SRAM yield. TSMC is still scheduling 5nm for 2020 but they did not say at what level EUV would be used. Probably because it depends on the EUV success at 7nm.
Also read: Top 10 Updates from the TSMC Technology Symposium, Part IShare this post via:
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