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Analog Bits is Supplying Analog Foundation IP on the Industry’s Most Advanced FinFET Processes

Analog Bits is Supplying Analog Foundation IP on the Industry’s Most Advanced FinFET Processes
by Mike Gianfagna on 12-02-2020 at 10:00 am

Analog Bits is Supplying Analog Foundation IP on the Industrys Most Advanced FinFET Processes

The industry recently concluded a series of technology events for the all the major foundries.  Done as virtual events this year, each one provided a significant update on technology platforms, roadmaps and ecosystem partnerships. These events are quite valuable to chip design teams who need to be aware of the latest in process, IP and EDA. With regard to the ecosystem, some companies will focus their efforts on one particular foundry. Supporting more than one can be a technologically daunting challenge. And then there are those companies with the capability for a broad focus. Analog Bits is one of those companies. What follows is a summary of its participation in these events. You will see that Analog Bits is supplying analog foundation IP on the industry’s most advanced FinFET processes.

TSMC Open Innovation Platform® Ecosystem Forum

The TSMC event was held on August 25, 2020. I’ve already covered in detail what Analog Bits presented at the TSMC event here.

GLOBALFOUNDRIES 2020 GTC

The GF event was held on September 24, 2020. At this event, Analog Bits announced a comprehensive foundation analog IP portfolio for the GF 12LP FinFET platform and 12LP+ solution for artificial intelligence, cloud computing, and high-end consumer SoCs. Availability includes silicon-proven IP on GF’s 12LP and design kits available for 12LP+IP.

The key IP features of Analog Bits offering for GF’s 12LP platform and 12LP+ solution included an integer and fractional PLL, ring oscillator-based PCIe 2/3 PLL, process voltage PVT sensors, and power on reset (POR) circuitry and LC oscillator-based PCIe 4/5 PLL for 12LP+.

Mahesh Tirupattur, executive vice president at Analog Bits, spoke at the event. His presentation was titled “Foundation Analog IP for Hi-Rel and Hi- Performance SoCs”. He covered:

  • System clocking solutions for high performance SoC’s
  • PCIe power and system benefits with integrated clocking
  • Sensors and novel new system solutions and silicon results for the aforementioned IP

GF’s 12LP platform and 12LP+ solution offers chip designers a best-in-class combination of performance, power and area, along with a set of key features, cost-efficient development and fast time-to-market for high-growth cloud and edge AI applications.

Mark Ireland, vice president of Ecosystem and Design Solutions at GF commented, “Our collaboration with Analog Bits is focused on enabling our mutual customers with proven IP to deliver innovative next-generation chip designs. The availability of Analog Bits’ IP on GLOBALFOUNDRIES 12LP platform and 12LP+ solution enables customers to further differentiate their products in AI, cloud, and high-end consumer applications.”

Samsung SAFE Forum 2020

The Samsung event was held on October 28, 2020. At this event, Analog Bits presented a portfolio of clocking, sensor, I/O and SERDES IP available on Samsung 32LP, 28LPP, 28FDSOI, 14LPP, 8LPP, 7LPP, 5LPE technologies. This portfolio includes:

  • Low power PLL
  • PCIe reference clock
  • Chip-to-chip I/O
  • Clock TX/RX
  • OSC pads
  • PVT sensor
  • Power supply glitch detectors
  • High lane count, low power, multi-protocol SERDES optimized for PCIe protocol

Alan Rogers, president and CTO at Analog Bits, presented “PCIe SERDES – Gen4/5 Enterprise Class SERDES and Lowest Power Gen3/4 Automotive and Consumer SERDES in Samsung 28nm to 7nm Processes” at the event. His presentation covered:

  • PCI Express SERDES markets needs
    • Consumer and enterprise
  • Analog Bits SERDES capabilities and application use
    • Low power full-rate architecture for consumer markets
    • High performance half-rate architecture for the enterprise market
  • Silicon results of PCIe Gen5
  • Collaboration and IP availability at Samsung

Mahesh Tirupattur presented “Differentiated Low Power Analog Foundation IP – A Key Differentiator of AI SoCs” as well. His presentation covered:

  • An example of an AI chip
  • Challenges and requirements of AI chips
  • Capabilities needed from analog foundation IPs
    • Clocking
    • Sensors
    • I/Os
  • Analog Bits analog foundation IP offering in FinFET
  • Partnership with Samsung

Jongshin Shin, Vice President of IP Development Team at Samsung Electronics commented, “Samsung is proud to be working with Analog Bits for ten years. Their quality and reputation for collaborative business practices have helped Samsung Foundry’s customers to succeed in the marketplace.”

Foundry events tend to be worldwide and Analog Bits maintains a busy schedule to support these events. If you’d like to catch their next presentation, you can follow their event schedule at this location. As a final note, there is a short and informative interview with Mahesh Tirupattur available here. In under five minutes, you can get a good overview of the company and begin to understand how Analog Bits is supplying analog foundation IP on the industry’s most advanced FinFET processes.

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