CEO Interview: Tim Ramsdale of Agile Analog

CEO Interview: Tim Ramsdale of Agile Analog
by Daniel Nenni on 09-10-2021 at 6:00 am

Tim Ramsdale Agile Analog

Tim joined Agile Analog shortly after its formation in 2017, alongside Founder, Michael Hulse, with a mission to change the way Analog IP was designed and delivered. Before joining Agile Analog as CEO, Tim served as General Manager, Imaging and Vision at Arm.  He has experience of delivering products in wireless, consumer, infrastructure… Read More


Package Pin-less PLLs Benefit Overall Chip PPA

Package Pin-less PLLs Benefit Overall Chip PPA
by Tom Simon on 08-19-2021 at 6:00 am

Pin less PLLs from Analog Bits

SOCs designed on advanced FinFET nodes like 7, 5 and 3nm call for silicon-validated physical analog IP for many critical functions. Analog blocks have always been node and process specific and their development has always been a challenge for SOC teams. Fortunately, there are well established and endorsed analog IP companies… Read More


Podcast EP8: A Look Inside Analog IP and Analog Bits

Podcast EP8: A Look Inside Analog IP and Analog Bits
by Daniel Nenni on 02-19-2021 at 10:00 am

Dan and Mike are joined by Mahesh Tirupattur, executive vice president at Analog Bits. Mahesh discussed how he found his way to analog IP design and his long association with Analog Bits. Effective strategies for analog IP design and deployment are discussed as well as leading edge applications for analog IP . Mahesh also provides… Read More


Analog Bits is Supplying Analog Foundation IP on the Industry’s Most Advanced FinFET Processes

Analog Bits is Supplying Analog Foundation IP on the Industry’s Most Advanced FinFET Processes
by Mike Gianfagna on 12-02-2020 at 10:00 am

Analog Bits is Supplying Analog Foundation IP on the Industrys Most Advanced FinFET Processes

The industry recently concluded a series of technology events for the all the major foundries.  Done as virtual events this year, each one provided a significant update on technology platforms, roadmaps and ecosystem partnerships. These events are quite valuable to chip design teams who need to be aware of the latest in process,… Read More


CEO Interview: Murilo Pilon Pessatti of Chipus Microelectronics

CEO Interview: Murilo Pilon Pessatti of Chipus Microelectronics
by Daniel Nenni on 09-21-2020 at 6:00 am

MuriloPessatti Photo

Murilo Pilon Pessatti is an Electrical Engineer with a MSEE in Analog IC design. He studied in Brazil at São Paulo University (USP) and earned a masters at Campinas State University (UNICAMP). Murilo then moved to Lisbon in Europe to work for ChipIdea, in the early 2000’s when the smartphone era was just taking off.

“I… Read More


White Paper – Mixed Signal Verification for Nanometer SOCs

White Paper – Mixed Signal Verification for Nanometer SOCs
by Tom Simon on 08-19-2020 at 10:00 am

Mixed signal SOCs

The number of touchpoints between analog and digital circuits in high performance SoCs is increasing. This is not a problem because it is possible to implement critical analog blocks directly on nanometer scale digital ICs. However, in many cases digital interfaces or digital feedback circuitry configures these analog blocks… Read More


Analog IP Migration, Optimization and Verification

Analog IP Migration, Optimization and Verification
by Admin on 03-26-2020 at 11:00 am

Thu, Mar 26, 2020 11:00 AM – 12:00 PM MDT

** Work email address required**

ABSTRACT: Semiconductor companies designing ICs for smart phones, automotive and industrial applications, CPUs, GPUs and memory components all employ teams of custom IC designers to create the highest performance chips that are as small as possible,… Read More


Webinar on Tools and Solutions for Analog IP Migration

Webinar on Tools and Solutions for Analog IP Migration
by Tom Simon on 03-17-2020 at 10:00 am

MunEDA flow for analog design porting

The commonly advanced reason for IP reuse is lower cost and shorter development time. However, IP reuse presents its own challenges, especially for analog designs. In the case of digital designs, once a new standard cell library is available, it is usually not too hard to resynthesize RTL to create new working silicon. For analog… Read More


56th DAC – In Depth Look at Analog IP Migration from MunEDA

56th DAC – In Depth Look at Analog IP Migration from MunEDA
by Tom Simon on 07-31-2019 at 10:00 am

Every year at DAC, in addition to the hubbub of the exhibit floor and the relatively short technical sessions, there are a number of tutorials that dive in depth into interesting topics. At the 56th DAC in Las Vegas this year, MunEDA offered an interesting tutorial on Analog IP migration and optimization. This is a key issue for large… Read More


CEO Interview: Ramy Iskander of Intento Design

CEO Interview: Ramy Iskander of Intento Design
by Daniel Nenni on 03-14-2018 at 7:00 am

One of the more interesting parts of blogging for SemiWiki is getting to know emerging EDA and IP companies from around the world. As I have mentioned before, there are some incredibly intelligent people in the fabless semiconductor ecosystem solving very complex problems. It is a two way exchange of course since we know the market… Read More