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Package Pin-less PLLs Benefit Overall Chip PPA

Package Pin-less PLLs Benefit Overall Chip PPA
by Tom Simon on 08-19-2021 at 6:00 am

SOCs designed on advanced FinFET nodes like 7, 5 and 3nm call for silicon-validated physical analog IP for many critical functions. Analog blocks have always been node and process specific and their development has always been a challenge for SOC teams. Fortunately, there are well established and endorsed analog IP companies like Analog Bits that provide high performance analog IP that is ready to use for just about every process. I had a conversation recently with Mahesh Tirupattur, executive VP of sales and marketing at Analog Bits, where we discussed their PLL portfolio. Clocking requirements have grown substantially, and this has led to diversity in their PLL product line.

Mahesh touched upon new PLLs needed for PCIe. Their PCIe Gen3 PHY is based on a ring oscillator and Gen4/5 PLL uses an LC tank. They have also added high performance PLLs for chip-to-chip interfaces that operate at 20GHz for advanced FinFET nodes. As further illustration of the diversity now required in PLLs he pointed to ultra-low power PLLs for IoT and radiation hardened chips for military and space applications. Not only have the number of types of PLLs for specific applications grown, but the sheer number of PLLs needed to provide clocking across and throughout an SOC has increased.

Historically, there have been technical limitations on where PLLs could be located due to their power supply requirements. This, in turn, leads to larger clock distribution networks that added complexity due to a host of factors. Longer clock lines require substantial area due to buffers and inverters necessary to maintain clock signal integrity. They also create noise issues. Switching on larger clocks consumes a significant percentage of SOC power and also can lead to aging related failures. However, placing PLLs closer to where they are needed introduces the need for added clock supply lines and external power pins.

Pin less PLLs from Analog Bits
Pin-less PLLs from Analog Bits

Mahesh talked about Analog Bits’ Patented Package Pin-less technology for advanced FinFET nodes that gives designers the freedom to locate PLLs and analog sensors where they are needed without concern for adding additional non-core voltage supply lines. These PLLs only need core supply voltage, so they are free from pad power bump restrictions. The result is lower power, less aging effects, lower pin count, less cross talk and reduced area.

While analog IP has often rightly been considered enabling technology because it provides needed functions, the benefits from Analog Bits’ Package Pin-less offering go far beyond that. It creates ripple effects that improve top line development goals and criteria. It’s impressive how seemingly mundane building blocks can actually make big differences.

Analog Bits has a rigorous program to design and qualify test silicon. They work with a broad range of foundries and have physical IP for many on the most advanced FinFET processes. They offer an attractive no-royalty business model. Mahesh told me that since they were founded in 1996 they have made over one thousand deliveries which have been used to fab literally billions of units. Their website offers much more information on their full line of analog IP, which includes on-chip sensors, PLLs, SerDes and more.

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