WP_Term Object
(
    [term_id] => 16855
    [name] => Sondrel
    [slug] => sondrel
    [term_group] => 0
    [term_taxonomy_id] => 16855
    [taxonomy] => category
    [description] => 
    [parent] => 386
    [count] => 6
    [filter] => raw
    [cat_ID] => 16855
    [category_count] => 6
    [category_description] => 
    [cat_name] => Sondrel
    [category_nicename] => sondrel
    [category_parent] => 386
)
            
Sondrel leaderboard 2
WP_Term Object
(
    [term_id] => 16855
    [name] => Sondrel
    [slug] => sondrel
    [term_group] => 0
    [term_taxonomy_id] => 16855
    [taxonomy] => category
    [description] => 
    [parent] => 386
    [count] => 6
    [filter] => raw
    [cat_ID] => 16855
    [category_count] => 6
    [category_description] => 
    [cat_name] => Sondrel
    [category_nicename] => sondrel
    [category_parent] => 386
)

Sondrel Creates a Unique Modelling Flow to Ensure Your ASIC Hits the Target

Sondrel Creates a Unique Modelling Flow to Ensure Your ASIC Hits the Target
by Mike Gianfagna on 08-19-2021 at 10:00 am

Sondrel Creates a Unique Modelling Flow to Ensure Your ASIC Hits the TargetDesigning an ASIC is little bit like trying to hit the bullseye, in the dark. I’ve spent several decades in the ASIC business I can tell you this is what it’s like from first-hand experience. When the design team sets out to build a custom chip to make their product better, faster, more robust, etc. (pick the words you like), there is tremendous excitement and optimism. The ideas at play are powerful and if a cost-effective chip could be built to realize the dream the world would beat a path to their door. All this euphoria gets dampened pretty quickly as the reality of complex chip design sets in. Can this chip really be built in the performance and cost envelope envisioned? As more details come to light, more challenges become clear. It’s a daunting problem that can drive even the most knowledgeable design teams crazy.  What if you could really see the future?  What if you could quickly build a model of the chip that you believed in? This would be a game-changer, and this is the topic I’ll discuss. Read on to see how Sondrel creates a unique modelling flow to ensure your ASIC hits the target. 

The Pieces

Sondrel recently announced unique modelling flow software to cut ASIC modelling time from months to a few days. This is headline news for sure. Let’s take a closer look at the parts of the solution to better understand the real impact. The announcement points out that:

It is important to model an SoC well in advance to avoid costly over design or insufficient performance and to create a hardware emulation on which representative end user applications can be run.

The balancing act at play here includes understanding performance, power, memory resources and the complex interconnect that will be required, along with a sense of die size and cost. Armed with this information, the design team can dial in an optimal strategy. Sometimes the data can also convince the team to cancel the project. Either way, forward visibility is a strategic advantage.

The real challenge with all this is time. A robust model that can truly inform decision-making can take months to build. A lot of design projects don’t have the luxury of this much time to decide on go/no go. So, there is a lot of shooting in the dark.

Until now.

Sondrel™ has created unique, proprietary modelling flow software, initially for use with Arm® and Synopsys® tools, that dramatically reduces the time to create a robust model from months to a few days. This appears to be an industry first, and the implications are significant.

The Impact

According to Graham Curren, Sondrel’s CEO, “we believe that we are unique in being able to provide such comprehensive information for architecting complex designs and at a level of detail and speed that our rivals cannot match. And, if we can use this with one of our predefined Architecting the Future™ IP platforms for the customer’s design, we can reduce time, risk and costs even more dramatically.”

The Architecting the Future IP platforms refers to Sondrel’s family of reference designs for major application areas. This is another way to reduce risk and ensure your design hits the target. Application areas supported include:

  • Video & data processing
  • ADAS and FuSa
  • IoT and edge processing

This family of reference designs can reduce design costs, risk, and time by up to 30% according to Sondrel. Modelling tools are available as standard products from leading vendors but what Sondrel does is wrap the vendor’s offerings with its own custom flow, creating a real competitive advantage.

The biggest benefit of the modelling flow’s dramatic reduction in the time to create a model is that Sondrel can provide customers with data on the likely performance of a proposed ASIC in a matter of days. This helps to quickly determine if the architecture proposed will hit the required target. If not, it is very easy and quick to run variants of the model simply by changing the settings of the existing model to decide which is the best one for the customer’s application use case.

For comparison, converging on a candidate architecture without Sondrel’s modelling flow tool would rely heavily on static spreadsheet modelling. This would take several weeks and then each variant of the model to evaluate different architectures would each take weeks as each variant model would have to be created from scratch. Overall, that could total a number of months.

And that’s the margin of victory in a fast-paced environment where time-to-market is everything.  You can now appreciate the impact when Sondrel creates a unique modelling flow to ensure your ASIC hits the target.

Share this post via:

Comments

There are no comments yet.

You must register or log in to view/post comments.