At advanced nodes such as 7 and 5nm, timing closure and sign off are becoming much more difficult than before at 16nm. One area of chips that has increased in complexity dramatically and who’s correct operation is essential for silicon success is the clock tree. If the clock tree has excessive jitter, it will throw off every timing parameter on the chip and can lead to failure. Clock jitter has become a much larger issue in particular because of the influence of simultaneous switching noise (SSN) and stress on the power deliver network (PDN), both of which have become difficult to manage with higher chip complexity and lower operating voltages.
Ansys recently broadcast an interesting webinar titled “Got Clock Jitter – It’s Worse Than You Think”, that explores the causes of clock jitter at advanced nodes and discusses their approach to providing effective analysis so that problems can be identified before tape out. The presenter, Vinayakam Subramanian, does an excellent job of discussing this important facet of chip design.
As I mentioned, SSN is a side effect caused by the operation of large numbers of densely packed transistors that causes dynamic loads on the chip’s power rails. PDNs have grown in complexity to provide the necessary voltage and current for gates on signal and on clock paths. However, it is always a challenge to assure that clock timing is not adversely affected. Vinayakam also points out that variation of ground rails causes different effects on gates than power rail variations. So, it is important to not only look at the voltage delta between the supply and ground, but to also evaluate ground bounce and supply droop independently.
According to Vinayakam, Static timing analysis (STA) tools aren’t up to the task of uncovering jitter issues. In the webinar he points to several reason for this. For starters they do not handle clock meshes, which are being used increasingly in new designs. Also, STA tools do not support inputs from tools that report power integrity. Likewise, they do not model the timing effects of ground bounce as distinct from power rail voltage drop.
SPICE has been another method of analyzing clocks, but there are serious limitations here too. SPICE might be fine for looking closely at individual clock paths. However, for full chip analysis runtimes become unmanageable. There is also a large effort required to setup SPICE runs for clock analysis.
In the webinar Ansys presents using their Clock FX tool to fully analyze for clock jitter. They start with pointing out that RedHawk-SC is a leading power integrity analysis tool, and provides the inputs needed to look closely at the clock tree while the chip operates dynamically. Using a combination of Dynamic Voltage Drop (DVD) information from RedHawk-SC, timing constraints and gate models, Clock FX can calculate jitter information across the entire clock network.
Their approach has some interesting advantages. For one, the gates in the clock tree do not need to be recharacterized at multiple voltages. Clock FX has built in capabilities to predict gate behavior across a range of voltages. Ansys claims they achieve SPICE level accuracy in a fraction of the time using their transient solver. Clock FX has been in production over numerous processes going back to 55nm and is in use up to 3nm today. Clock FX also supports execution on modern day compute farms. There is also the ability to export run data to the Ansys SeaScape big data analysis environment.
The webinar goes into more detail about the dynamic and transient results that their clock analysis flow provides. Ansys has a strong pedigree in the area of power integrity and also in the area of timing analysis. If this solution sounds interesting, more information about their clock analysis solution is available on the Ansys website.
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