Have STA and SPICE Run Out of Steam for Clock Analysis?

Have STA and SPICE Run Out of Steam for Clock Analysis?
by Tom Simon on 08-20-2021 at 6:00 am

Ansys clock jitter analysis

At advanced nodes such as 7 and 5nm, timing closure and sign off are becoming much more difficult than before at 16nm. One area of chips that has increased in complexity dramatically and who’s correct operation is essential for silicon success is the clock tree. If the clock tree has excessive jitter, it will throw off every timing… Read More