In the good old days the clock signal looked like a square wave , and had a voltage swing of 5 volts, however with 7nm technology the clock signals can now look more like a sawtooth signal and may not actually reach the full Vdd value of 0.65V inside the core of a chip. I’ll cover some of the semiconductor market trends, and then challenges… Read More
Synchronous circuits dominate the electronic world because clocking eases the design of circuits compared to asynchronous circuits. At the same time, clocking also introduces its share of challenges to overcome. No wonder, a tremendous amount of time and effort have been spent over the years on developing and implementing … Read More
At advanced nodes such as 7 and 5nm, timing closure and sign off are becoming much more difficult than before at 16nm. One area of chips that has increased in complexity dramatically and who’s correct operation is essential for silicon success is the clock tree. If the clock tree has excessive jitter, it will throw off every timing… Read More
Date and time:
Thursday, July 1, 2021 12:00 am
Eastern Daylight Time (New York, GMT-04:00)
Thursday, July 1, 2021 12:00 pm
Taipei Time (Taipei, GMT+08:00)
Thursday, July 1, 2021 1:00 pm
Korea Time (Seoul, GMT+09:00)
Thursday, July 1, 2021 1:00 pm
Japan Time (Tokyo, GMT+09:00)
Duration: 1 hour
Description:
Today’s advanced… Read More
Event status: Not started (Register)
Date and time:
Tuesday, June 29, 2021 12:00 pm
Eastern Daylight Time (New York, GMT-04:00)
Tuesday, June 29, 2021 12:00 pm
Eastern Daylight Time (New York, GMT-04:00)
Tuesday, June 29, 2021 5:00 pm
GMT Summer Time (London, GMT+01:00)
Tuesday, June 29, 2021 6:00 pm
Europe Summer Time (Brussels,… Read More
I wrote recently about a yield problem which mobile vendors have been finding for devices built in advanced technologies. This was a performance issue (the devices worked fine at lower clock speeds), pointing to a discrepancy in some devices between predicted and observed timing. These were experienced design teams, using state… Read More
Jitter issues in SOC’s reside at the crossroads of analog and digital design. Digital designers would prefer to live in a world of clocks that are free from jitter effects. At the same time, analog designers can build PLL’s that are precise and finely tuned. However, when a perfectly working PLL is inserted into an SOC, things can … Read More
