Have STA and SPICE Run Out of Steam for Clock Analysis?

Have STA and SPICE Run Out of Steam for Clock Analysis?
by Tom Simon on 08-20-2021 at 6:00 am

Ansys clock jitter analysis

At advanced nodes such as 7 and 5nm, timing closure and sign off are becoming much more difficult than before at 16nm. One area of chips that has increased in complexity dramatically and who’s correct operation is essential for silicon success is the clock tree. If the clock tree has excessive jitter, it will throw off every timing… Read More


Ansys Webinar: Got Clock Jitter? – It’s Worse Than You Think (Asia)

Ansys Webinar: Got Clock Jitter? – It’s Worse Than You Think (Asia)
by Admin on 07-01-2021 at 12:00 am

Date and time:

Thursday, July 1, 2021 12:00 am
Eastern Daylight Time (New York, GMT-04:00)

Thursday, July 1, 2021 12:00 pm
Taipei Time (Taipei, GMT+08:00)

Thursday, July 1, 2021 1:00 pm
Korea Time (Seoul, GMT+09:00)

Thursday, July 1, 2021 1:00 pm
Japan Time (Tokyo, GMT+09:00)

Duration: 1 hour

Description:

Today’s advanced… Read More


Ansys Webinar: Got Clock Jitter? – It’s Worse Than You Think (North America and Europe)

Ansys Webinar: Got Clock Jitter? – It’s Worse Than You Think (North America and Europe)
by Admin on 06-29-2021 at 12:00 am

Event status: Not started (Register)

Date and time:

Tuesday, June 29, 2021 12:00 pm
Eastern Daylight Time (New York, GMT-04:00)

Tuesday, June 29, 2021 12:00 pm
Eastern Daylight Time (New York, GMT-04:00)

Tuesday, June 29, 2021 5:00 pm
GMT Summer Time (London, GMT+01:00)

Tuesday, June 29, 2021 6:00 pm
Europe Summer Time (Brussels,… Read More


Peering Over the Timing Edge

Peering Over the Timing Edge
by Bernard Murphy on 05-03-2018 at 7:00 am

I wrote recently about a yield problem which mobile vendors have been finding for devices built in advanced technologies. This was a performance issue (the devices worked fine at lower clock speeds), pointing to a discrepancy in some devices between predicted and observed timing. These were experienced design teams, using state… Read More


Understanding Sources of Clock Jitter Critical for SOC’s

Understanding Sources of Clock Jitter Critical for SOC’s
by Tom Simon on 05-29-2017 at 12:00 pm

Jitter issues in SOC’s reside at the crossroads of analog and digital design. Digital designers would prefer to live in a world of clocks that are free from jitter effects. At the same time, analog designers can build PLL’s that are precise and finely tuned. However, when a perfectly working PLL is inserted into an SOC, things can … Read More